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    Test pad and probe card for wafer acceptance testing and other applications
    2.
    发明申请
    Test pad and probe card for wafer acceptance testing and other applications 审中-公开
    测试垫和探针卡，用于晶圆验收测试等应用

    公开(公告)号：US20060109014A1

    公开(公告)日：2006-05-25

    申请号：US10996242

    申请日：2004-11-23

    申请人： Te-Tsung Chao ,  Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    发明人： Te-Tsung Chao ,  Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2891 ,  G01R31/2884

    摘要： A probe card having a member for sending and receiving electrical signals for operational testing of a semiconductor integrated circuit, and a plurality of probe pins extending from the member in a manner which causes free ends of the pins to contact wafer test pads substantially across a maximum dimension of the pads. Also, a test pad for a wafer or a substrate having a pad of electrically conductive material disposed in an area between seal rings of the wafer or substrate, the pad having a shape and/or a rotational orientation within the area between the seal rings that minimizes pad material immediately adjacent the seal rings. Further, a test pad for a wafer or substrate including a passivation layer disposed thereover, the test pad formed of a layer of electrically conductive material and disposed in an opening in the passivation layer, the opening disposed over an uppermost metal layer of the wafer or substrate, the opening and the test pad dimensioned so that the test pad does not contact the passivation layer. Still further, a protection structure for a wafer die core comprising a wafer including a passivation layer and a test pad extending through the passivation layer, and a trench in the passivation layer adjacent to an edge of the test pad.

    摘要翻译： 具有用于发送和接收用于半导体集成电路的操作测试的电信号的构件的探针卡，以及多个探针，所述探针从所述构件延伸，使得所述引脚的自由端基本上跨越最大值接触晶片测试垫 垫的尺寸。 此外，用于晶片或基板的测试焊盘，其具有设置在晶片或基板的密封环之间的区域中的导电材料焊盘，该焊盘在密封环之间的区域内具有形状和/或旋转取向， 最小化紧邻密封环的垫材料。 此外，包括设置在其上的钝化层的晶片或衬底的测试焊盘，所述测试焊盘由导电材料层形成并设置在钝化层的开口中，所述开口设置在晶片的最上层的金属层上，或 衬底，开口和测试焊盘的尺寸设计成使得测试焊盘不接触钝化层。 此外，晶片芯片的保护结构包括包括钝化层的晶片和延伸穿过钝化层的测试焊盘，以及钝化层中邻近测试焊盘边缘的沟槽。

    Process for separating dies on a wafer
    3.
    发明授权
    Process for separating dies on a wafer 有权
    用于在晶片上分离模具的工艺

    公开(公告)号：US06849523B2

    公开(公告)日：2005-02-01

    申请号：US10387285

    申请日：2003-03-12

    申请人： Te-Tsung Chao ,  Shu-Shen Chiu

    发明人： Te-Tsung Chao ,  Shu-Shen Chiu

    IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/78

    CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327

    摘要： A process for separating IC dies from a wafer substrate. In one embodiment, complete separation channels are initially cut through the wafer between dies along one axis. Next, partial separation channels are cut into the wafer along an intersecting axis, leaving wafer material connecting adjacent dies. In another embodiment, partial separation channels are cut into the wafer along one axis, after which complete separation channels are cut through the wafer along the intersecting axis. In still another embodiment, partial separation channels are cut along both axes.

    摘要翻译： 用于从晶片衬底分离IC管芯的工艺。 在一个实施例中，完全分离通道最初沿着一个轴线切割穿过管芯之间的晶片。 接下来，沿着交叉轴将部分分离通道切入晶片，留下晶片材料连接相邻的模具。 在另一个实施例中，沿着一个轴将部分分离通道切入晶片，之后沿着相交轴线将整个分离通道切割通过晶片。 在另一个实施例中，沿两个轴切割部分分离通道。

    Method for positioning bond pads in a semiconductor die
    4.
    发明授权
    Method for positioning bond pads in a semiconductor die 有权
    用于在半导体管芯中定位接合焊盘的方法

    公开(公告)号：US06405357B1

    公开(公告)日：2002-06-11

    申请号：US09562904

    申请日：2000-05-02

    申请人： Te Tsung Chao ,  Hui Chin Fang

    发明人： Te Tsung Chao ,  Hui Chin Fang

    IPC分类号： G06F1750

    CPC分类号： H01L24/06 ,  G06F17/5068 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2224/45099

    摘要： A method for positioning bond pads in a semiconductor die comprises the steps of (I) setting parameters including (a) setting a baseline pad pitch to a first value, (b) setting a first pad position equal to a first pad value and (c) providing a focal point; (II) determining a first angle between a first line through a center of the first pad position and the focal point and a second line through a center of the semiconductor die and normal to the edge; (III) determining a first pad spacing increment value equal to the first value divided by a cosine of the first angle; (IV) setting a second pad position equal to a second pad value, wherein the second pad value at least equals the first pad value plus the first value if both of the first bond pad and the second bond pad are ground pad or power pad with the same potential, else the second pad value at least equals the first pad value plus the first pad spacing increment value; and (V) using the first and second pad values to respectively position a first bond pad and a second bond pad along the edge of the semiconductor die. Beginning from the bond pad closest to the die corner, optimized positions of bond pads can be determined by repeating steps I to V.

    摘要翻译： 一种用于在半导体管芯中定位接合焊盘的方法包括以下步骤：（I）设置参数，其包括（a）将基准焊盘间距设置为第一值，（b）设置等于第一焊盘值的第一焊盘位置和（c ）提供协调中心 （II）确定通过第一焊盘位置的中心的第一行与焦点之间的第一角度，以及穿过半导体管芯的中心并垂直于边缘的第二线; （III）确定等于第一值的第一焊盘间隔增量值除以第一角度的余弦值; （IV）设置等于第二焊盘值的第二焊盘位置，其中如果所述第一焊盘和所述第二接合焊盘都是接地焊盘或电源焊盘，则所述第二焊盘值至少等于所述第一焊盘值加上所述第一焊盘值， 相同的电位，否则第二焊盘值至少等于第一焊盘值加上第一焊盘间隔增量值; 和（V）使用第一和第二焊盘值分别沿着半导体管芯的边缘定位第一接合焊盘和第二接合焊盘。 从最靠近模具角的接合焊盘开始，可以通过重复步骤I至V来确定焊盘的优化位置。