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公开(公告)号：US5734199A
公开(公告)日：1998-03-31
申请号：US767778
申请日：1996-12-17
CPC分类号： H01L25/50 , H01L22/20 , H01L22/32 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L2224/13562 , H01L2224/13644 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2224/75 , H01L2224/7525 , H01L2224/75301 , H01L2224/83192 , H01L2224/83224 , H01L2224/83859 , H01L2224/83874 , H01L2225/06513 , H01L2225/06582 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/381
摘要： The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.
摘要翻译： 具有第一功能元件的第一半导体芯片的主表面形成有用于测试第一功能元件的电特性的第一测试电极和与第一功能元件电连接的第一连接电极。 具有第二功能元件的第二半导体芯片的主表面形成有用于测试第二功能元件的电特性的第二测试电极和与第二功能元件电连接的第二连接电极。 通过使用绝缘树脂将第一半导体芯片和第二半导体芯片集成在一起，形成在第一连接电极上的第一凸块与形成在第二连接电极上的第三凸块接合。
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公开(公告)号：US5811351A
公开(公告)日：1998-09-22
申请号：US978270
申请日：1997-11-25
IPC分类号： H01L21/66 , H01L21/98 , H01L23/58 , H01L25/065 , H01L21/44
CPC分类号： H01L25/50 , H01L22/20 , H01L22/32 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L2224/13562 , H01L2224/13644 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2224/75 , H01L2224/7525 , H01L2224/75301 , H01L2224/83192 , H01L2224/83224 , H01L2224/83859 , H01L2224/83874 , H01L2225/06513 , H01L2225/06582 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/381
摘要： The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.
摘要翻译： 具有第一功能元件的第一半导体芯片的主表面形成有用于测试第一功能元件的电特性的第一测试电极和与第一功能元件电连接的第一连接电极。 具有第二功能元件的第二半导体芯片的主表面形成有用于测试第二功能元件的电特性的第二测试电极和与第二功能元件电连接的第二连接电极。 通过使用绝缘树脂将第一半导体芯片和第二半导体芯片集成在一起，形成在第一连接电极上的第一凸块与形成在第二连接电极上的第三凸块接合。
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公开(公告)号：US20070090986A1
公开(公告)日：2007-04-26
申请号：US11583848
申请日：2006-10-20
申请人： Shigeyuki Komatsu , Ichiro Yamane
发明人： Shigeyuki Komatsu , Ichiro Yamane
IPC分类号： H03M1/12
CPC分类号： H03M1/0827 , H03M1/468 , H03M1/68 , H03M1/785 , H03M1/804
摘要： An analog-digital converter includes an analog switch on a semiconductor substrate, the analog switch having a P-channel transistor and an N-channel transistor; and a capacitive element having a first electrode and a second electrode. The first electrode and the second electrode are formed in a region in a layer different from a layer of the analog switch, the region extending over the analog switch. The first electrode and the second electrode have a comb-shaped pattern different from an arrangement pattern of the source regions and the drain regions of the P-channel transistor and the N-channel transistor.
摘要翻译： 模拟数字转换器包括半导体衬底上的模拟开关，模拟开关具有P沟道晶体管和N沟道晶体管; 以及具有第一电极和第二电极的电容元件。 第一电极和第二电极形成在与模拟开关的层不同的区域中，该区域在模拟开关上延伸。 第一电极和第二电极具有与P沟道晶体管和N沟道晶体管的源极区域和漏极区域的布置图案不同的梳状图案。
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公开(公告)号：US5821625A
公开(公告)日：1998-10-13
申请号：US636651
申请日：1996-04-23
申请人： Takayuki Yoshida , Takashi Otsuka , Hiroaki Fujimoto , Tadaaki Mimura , Ichiro Yamane , Takio Yamashita , Toshio Matsuki , Yoshiaki Kasuga
发明人： Takayuki Yoshida , Takashi Otsuka , Hiroaki Fujimoto , Tadaaki Mimura , Ichiro Yamane , Takio Yamashita , Toshio Matsuki , Yoshiaki Kasuga
IPC分类号： H01L21/56 , H01L23/552 , H01L25/065 , H01L25/18 , H01L23/02 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/552 , H01L24/29 , H01L25/18 , H01L2224/1147 , H01L2224/16145 , H01L2224/16225 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/73203 , H01L2224/83102 , H01L2224/83192 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06527 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/14 , H01L2924/30105 , H01L2924/30107
摘要： The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.
摘要翻译： 本发明减少串扰，其是由于在第一半导体芯片的各个布线层的每一个中运行的信号与以小间隙堆叠在表面之间的第二半导体芯片之间的干扰而发生的。 该半导体器件包括在主表面上具有第一电极焊盘2和第一布线层9的第一半导体芯片1和第二半导体芯片5，第二半导体芯片5在主表面中具有第二电极焊盘6和第二布线层10 第一个半导体芯片。 凸块4被设置用于将第一电极焊盘2和第二电极焊盘6电耦合在一起。 绝缘层8设置在第一半导体芯片1和第二半导体芯片5的主表面之间。导电层7设置在第一半导体芯片和第二半导体芯片的主要相对表面之间。
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公开(公告)号：US20110291767A1
公开(公告)日：2011-12-01
申请号：US13122694
申请日：2010-07-22
申请人： Shinji Ishikawa , Ichiro Yamane
发明人： Shinji Ishikawa , Ichiro Yamane
IPC分类号： H03B5/32
CPC分类号： H03B5/36 , H03B5/06 , H03B2200/0046 , H03B2200/0094 , H03K3/0307 , H03L3/00
摘要： An oscillator circuit comprises a piezoelectric vibrator, an amplifier device including inverters provided in a plurality of stages, and an inverter control device. The inverters provided in the plurality of stages includes a performance-variable inverter configured which is operational in both of an initial phase of oscillation startup and a post-startup phase where the oscillation is stabilized and capable of a variable performance depending on whether the initial phase of oscillation startup or the post-startup phase where the oscillation is stabilized, and an ON/OFF inverter which is operational in the initial phase of oscillation startup and disconnected in the post-startup phase where the oscillation is stabilized. The inverter control device have the performance-variable inverter and the ON/OFF inverter both operational and lowers the performance of the performance-variable inverter in the initial phase of oscillation startup, and the inverter control device disconnects the ON/OFF inverter and increases the performance of the performance-variable inverter in the post-startup phase where the oscillation is stabilized.
摘要翻译： 振荡电路包括压电振动器，包括设置在多个级中的反相器的放大器装置和逆变器控制装置。 设置在多级中的逆变器包括：性能可变逆变器，其配置为在振荡启动的初始阶段和振荡稳定的后启动阶段两者中都可操作，并且能够根据初始阶段 振荡启动或振荡稳定的后启动阶段，以及在振荡稳定初始阶段中振荡启动的初始阶段和断开的ON / OFF逆变器。 逆变器控制装置具有性能可变的变频器和ON / OFF变频器，在起动初始阶段均可使运行性能可变变频器的性能降低，变频器控制装置断开ON / OFF变频器， 性能可变的逆变器在振荡稳定的后启动阶段的性能。
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公开(公告)号：US20080258405A1
公开(公告)日：2008-10-23
申请号：US12078508
申请日：2008-04-01
申请人： Masatoshi Okada , Iwao Taira , Tadashi Abiko , Yosuke Kondo , Kazuki Takeno , Ichiro Yamane
发明人： Masatoshi Okada , Iwao Taira , Tadashi Abiko , Yosuke Kondo , Kazuki Takeno , Ichiro Yamane
CPC分类号： F16J15/3232 , F02M59/442 , F04B53/164 , F16J15/002 , F16J15/3204 , F16J15/3208 , F16J15/3236
摘要： A high performance sealing device having an excellent pressure resistance and realizing a prevention of damage. The sealing device usable at a working pressure of 0 to 2 MPa, and not damaged. even if the pressure of high-pressure fuel of 5 MPa or higher is applied thereto, wherein high pressure fuel on the high pressure side H is sealed by a first seal part 2, oil from a cam side on a low pressure side L is sealed by a second seal part 3, and the fuel slightly leaked due to failure of scraping at the first seal part is sealed by the second seal part to form a dual seal structure, and a resin ring 21 coming into slidable sealing contact with a shaft 10 is used in the first seal part 2, whereby abnormal abrasion does not occur even when fuel having less lubricity is used, and the durability of the seal is increased.
摘要翻译： 一种高性能的密封装置，具有优异的耐压性和防止损伤。 密封装置可在0〜2MPa的工作压力下使用，不会损坏。 即使施加5MPa以上的高压燃料的压力，由高压侧H的高压燃料被第一密封部2密封，来自低压侧L的凸轮侧的油被密封 通过第二密封部3，由于第一密封部的刮擦不良而稍微漏出的燃料被第二密封部密封，形成双重密封结构，并且与轴10可滑动地密封接触的树脂环21 用于第一密封部2，即使使用润滑性较差的燃料，也不会发生异常磨损，并且密封件的耐久性提高。
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公开(公告)号：US07918463B2
公开(公告)日：2011-04-05
申请号：US12230708
申请日：2008-09-03
申请人： Hidenori Arai , Kazuki Takeno , Ichiro Yamane , Shinobu Munekata , Katsumi Yamashina , Masaru Watanabe
发明人： Hidenori Arai , Kazuki Takeno , Ichiro Yamane , Shinobu Munekata , Katsumi Yamashina , Masaru Watanabe
IPC分类号： F16J15/32
CPC分类号： F16F9/36 , F16J15/3232 , F16J15/3236 , F16J15/56
摘要： A reciprocating seal used, for example, for a shock absorber. A main seal lip has a two-step lip structure including a first lip and a second lip and a plurality of protrusions extending in the direction of the shaft are formed on a sliding contact surface of the second lip, thereby improving frictional force characteristics and, at the same time, improving sealing performance.
摘要翻译： 用于例如用于减震器的往复式密封件。 主密封唇具有包括第一唇缘和第二唇缘的两段唇缘结构，并且在第二唇缘的滑动接触表面上形成有在轴的方向上延伸的多个突起，从而提高摩擦力特性， 同时提高密封性能。
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公开(公告)号：US07633351B2
公开(公告)日：2009-12-15
申请号：US11892444
申请日：2007-08-23
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03L1/00 , H03L7/0995
摘要： A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.
摘要翻译： 差分放大电路包括：由第一和第二晶体管组成的差分晶体管对; 连接到一个端子处的第一和第二晶体管的连接点的第一电阻和另一个端子处的第一电压节点的第一电阻; 分别设置在第一和第二晶体管之间的第二和第三电阻和第二电压节点; 以及分别连接到第二和第三电阻的第一和第二无源电路，无源电路的负载特性根据提供的控制信号而变化。 环形振荡器由以循环连接的多个这样的差分放大器电路组成。
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公开(公告)号：US20090134586A1
公开(公告)日：2009-05-28
申请号：US12230708
申请日：2008-09-03
申请人： Hidenori Arai , Kazuki Takeno , Ichiro Yamane , Shinobu Munekata , Katsumi Yamashina , Masaru Watanabe
发明人： Hidenori Arai , Kazuki Takeno , Ichiro Yamane , Shinobu Munekata , Katsumi Yamashina , Masaru Watanabe
IPC分类号： F16J15/32
CPC分类号： F16F9/36 , F16J15/3232 , F16J15/3236 , F16J15/56
摘要： The present invention relates to a reciprocating seal used, for example, for a shock absorber. A main seal lip 32 has a two-step lip structure including a first lip 32a and a second lip 32b and a plurality of protrusions 34 extending in the direction of the shaft are formed on a sliding contact surface of the second lip 32b, thereby improving frictional force characteristics and, at the same time, improving sealing performance.
摘要翻译： 本发明涉及例如用于减震器的往复式密封件。 主密封唇32具有包括第一唇缘32a和第二唇缘32b的两阶唇缘结构，并且在第二唇缘32b的滑动接触表面上形成有沿轴向方向延伸的多个突起34，从而改善 摩擦力特性，同时提高密封性能。
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公开(公告)号：US06600683B2
公开(公告)日：2003-07-29
申请号：US09953555
申请日：2001-09-17
申请人： Ichiro Yamane
发明人： Ichiro Yamane
IPC分类号： G11C700
CPC分类号： G06F21/71 , G06F2221/2149
摘要： A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an input and an output to each external functional block in accordance with the logical content of the memory, wherein a user is allowed to validate use of a necessary external functional block and to invalidate use of an unnecessary external functional block.
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