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公开(公告)号：US20120160547A1
公开(公告)日：2012-06-28
申请号：US12764993
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
CPC分类号： H05K3/462 , H05K1/167 , H05K3/4069 , H05K3/4623 , H05K3/4632 , H05K2203/0191 , H05K2203/061 , H05K2203/063
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。
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公开(公告)号：US20120031649A1
公开(公告)日：2012-02-09
申请号：US12764997
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H05K1/02
CPC分类号： H05K3/4069 , H05K3/4614 , H05K3/462 , H05K3/4623 , H05K2203/063
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。
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3.发明申请Method of making high density interposer and electronic package utilizing same 有权制造高密度插入件的方法和使用其的电子封装公开(公告)号：US20110126408A1
公开(公告)日：2011-06-02
申请号：US12592734
申请日：2009-12-01
CPC分类号： H05K3/4623 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/19 , H01L24/20 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H05K3/0035 , H05K3/305 , H05K2201/0154 , H05K2201/10378 , H05K2201/10674 , H05K2203/061 , H05K2203/1469 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , H01L2924/00012 , H01L2924/00
摘要： A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.
摘要翻译： 一种制造电子封装的方法，其设计用于互连电子器件（例如，半导体芯片）的导体的高密度图案和托管电路化基板（例如，芯片载体，PCB）的导体的较不致密的图案。 在一个实施例中，该方法包括将芯片接合到单个电介质层，在该层的一个表面上形成高密度图案的导体，在该层中形成开口，然后沉积冶金以形成期望的电路图案， 接合并且电耦合到另一托管基板上的对应图案。 根据本发明的另一个实施例，提供了一种使用双层插入器的电子封装。 还提供了使用根据本发明的教导制造的电子封装制造电路化基板组件的方法。
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公开(公告)号：US20120160544A1
公开(公告)日：2012-06-28
申请号：US12764994
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
CPC分类号： H05K3/4623 , H05K1/092 , H05K3/4053 , H05K3/4614 , H05K3/4691 , H05K2203/061
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。
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5.发明授权Electronic package including high density interposer and circuitized substrate assembly utilizing same 有权电子封装包括高密度插入器和利用其的电路化基板组件公开(公告)号：US08405229B2
公开(公告)日：2013-03-26
申请号：US12592682
申请日：2009-11-30
IPC分类号： H01L29/40
CPC分类号： H01L23/49833 , H01L23/49822 , H01L23/49827 , H01L24/19 , H01L24/20 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.
摘要翻译： 一种用于将包装的电子设备（例如，半导体芯片）的导体的高密度图案互连到电路化基板（例如，PCB）上的较不致密的导体图案的电子封装，该封装在一个实施例中包括单个 薄的电介质层（例如，Kapton），其中具有高密度图案的开口和相对表面上的电路图案，其包括导体的高密度图案和不太密集的导体图案。 导电构件位于开口中，以将电子装置的导体与包装件定位在其上的电路化衬底的导体电互连。 在另一个实施例中，插入器包括结合到第一介质层的第二电介质层，其中导电构件延伸穿过第二层以连接到较小密集的电路化衬底导体图案。 还提供了使用本发明的电子封装件的电路化基板组件。
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6.发明授权Method of making high density interposer and electronic package utilizing same 有权制造高密度插入件的方法和使用其的电子封装公开(公告)号：US08245392B2
公开(公告)日：2012-08-21
申请号：US12592734
申请日：2009-12-01
CPC分类号： H05K3/4623 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/19 , H01L24/20 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H05K3/0035 , H05K3/305 , H05K2201/0154 , H05K2201/10378 , H05K2201/10674 , H05K2203/061 , H05K2203/1469 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , H01L2924/00012 , H01L2924/00
摘要： A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.
摘要翻译： 一种制造电子封装的方法，其设计用于互连电子器件（例如，半导体芯片）的导体的高密度图案和托管电路化基板（例如，芯片载体，PCB）的导体的较不致密的图案。 在一个实施例中，该方法包括将芯片接合到单个电介质层，在该层的一个表面上形成高密度图案的导体，在该层中形成开口，然后沉积冶金以形成期望的电路图案， 接合并且电耦合到另一托管基板上的对应图案。 根据本发明的另一个实施例，提供了一种使用双层插入器的电子封装。 还提供了使用根据本发明的教导制造的电子封装制造电路化基板组件的方法。
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7.发明申请Electronic package including high density interposer and circuitized substrate assembly utilizing same 有权电子封装包括高密度插入器和利用其的电路化基板组件公开(公告)号：US20110127664A1
公开(公告)日：2011-06-02
申请号：US12592682
申请日：2009-11-30
IPC分类号： H01L23/48 , H01L23/498
CPC分类号： H01L23/49833 , H01L23/49822 , H01L23/49827 , H01L24/19 , H01L24/20 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.
摘要翻译： 一种用于将包装的电子设备（例如，半导体芯片）的导体的高密度图案互连到电路化基板（例如，PCB）上的较不致密的导体图案的电子封装，该封装在一个实施例中包括单个 薄的电介质层（例如，Kapton），其中具有高密度图案的开口和相对表面上的电路图案，其包括导体的高密度图案和不太密集的导体图案。 导电构件位于开口中，以将电子装置的导体与包装件定位在其上的电路化衬底的导体电互连。 在另一个实施例中，插入器包括结合到第一介质层的第二电介质层，其中导电构件延伸穿过第二层以连接到较小密集的电路化衬底导体图案。 还提供了使用本发明的电子封装件的电路化基板组件。
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公开(公告)号：US20120015532A1
公开(公告)日：2012-01-19
申请号：US12837640
申请日：2010-07-16
申请人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
发明人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
CPC分类号： H05K3/3436 , H05K1/111 , H05K2201/10378 , Y02P70/613 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/4919
摘要： A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.
摘要翻译： 柔性，高密度贴花及其在柔性芯片载体和印刷线路板之间形成可拆卸电互连的方法。 柔性贴花在第一表面上具有细间距焊盘，并且在第二表面上具有比微细间距更宽的间距的焊盘，设计成电连接到半导体器件的第一表面上的细间距焊盘和较宽间距 第二表面上的焊盘被设计成电连接到印刷线路板等。 第一表面上的焊盘通过柔性贴花中的一个或多个绝缘水平导电地连接到第二表面上的焊盘。
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9.发明授权公开(公告)号：US08240031B2
公开(公告)日：2012-08-14
申请号：US12837640
申请日：2010-07-16
申请人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
发明人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
IPC分类号： H05K3/30
CPC分类号： H05K3/3436 , H05K1/111 , H05K2201/10378 , Y02P70/613 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/4919
摘要： A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.
摘要翻译： 柔性，高密度贴花及其在柔性芯片载体和印刷线路板之间形成可拆卸电互连的方法。 柔性贴花在第一表面上具有细间距焊盘，并且在第二表面上具有比微细间距更宽的间距的焊盘，设计成电连接到半导体器件的第一表面上的细间距焊盘和较宽间距 第二表面上的焊盘被设计成电连接到印刷线路板等。 第一表面上的焊盘通过柔性贴花中的一个或多个绝缘水平导电地连接到第二表面上的焊盘。
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公开(公告)号：US20130025839A1
公开(公告)日：2013-01-31
申请号：US13189980
申请日：2011-07-25
申请人： Frank Egitto , Voya R. Markovich , Varaprasad V. Calmidi , Timothy Antesberger , William E. Wilson
发明人： Frank Egitto , Voya R. Markovich , Varaprasad V. Calmidi , Timothy Antesberger , William E. Wilson
CPC分类号： H01L23/145 , F28F2013/006 , H01L23/3677 , H01L23/49822 , H01L23/49894 , H01L24/16 , H01L2224/131 , H01L2224/16235 , H01L2224/81191 , H01L2224/81192 , H01L2924/12042 , H05K1/0206 , H05K3/4679 , Y10T29/49826 , Y10T428/24322 , H01L2924/014 , H01L2924/00
摘要： An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.
摘要翻译： 一种能够通过使用延伸穿过衬底的平行的线性共同导热开口，通过其整个厚度提供有效的热传递的有机衬底，该衬底具有结合在一起的细介电层以形成一体的衬底结构。 该结构适于通过有效地将热量从部件传递到位于相对侧的冷却结构来辅助提供一侧的高温电气部件的冷却。 还提供制造基板的方法，以及包括基板，部件和冷却结构的电气组件。
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