公开(公告)号：US09276100B2

公开(公告)日：2016-03-01

申请号：US13294740

申请日：2011-11-11

Applicant: Hiroshi Endo ,  Toshihiro Ohki ,  Toshihide Kikkawa

Inventor： Hiroshi Endo ,  Toshihiro Ohki ,  Toshihide Kikkawa

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7839 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257

Abstract: A semiconductor device includes a first semiconductor layer disposed over a substrate, a second semiconductor layer disposed over the first semiconductor layer, a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer, an insulating film disposed over the gate recess and the second semiconductor layer, a gate electrode disposed over the gate recess with the insulating film therebetween, and a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer, whereby a central portion of the gate recess is higher than a peripheral portion of the gate recess.

Abstract translation: 半导体器件包括设置在衬底上的第一半导体层，设置在第一半导体层上的第二半导体层，通过在第一半导体上的预定区域中去除一部分或全部第二半导体层而设置的栅极凹槽 设置在所述栅极凹部和所述第二半导体层上的绝缘膜，设置在所述栅极凹部上方的绝缘膜的栅电极，以及设置在所述第一半导体层或所述第二半导体层上的源电极和漏电极， 从而栅极凹部的中心部分比栅极凹部的周边部分高。

公开(公告)号：US08816408B2

公开(公告)日：2014-08-26

申请号：US12721052

申请日：2010-03-10

Applicant: Kozo Makiyama ,  Toshihide Kikkawa

Inventor： Kozo Makiyama ,  Toshihide Kikkawa

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/20 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7843

Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.

Abstract translation: 化合物半导体器件包括化合物半导体层叠结构; 源电极，漏电极和形成在化合物半导体层叠结构上的栅电极; 在所述源电极和所述栅电极之间并且包括硅的所述化合物半导体层叠结构上形成的第一保护膜; 以及形成在所述漏电极和所述栅电极之间的所述化合物半导体层叠结构上并且包含比所述第一保护膜更多的硅的第二保护膜。

公开(公告)号：US08765554B2

公开(公告)日：2014-07-01

申请号：US13325972

申请日：2011-12-14

Applicant: Tadahiro Imada ,  Toshihide Kikkawa

Inventor： Tadahiro Imada ,  Toshihide Kikkawa

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66462 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/181 ,  H03F1/3247 ,  H03F1/523 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/204 ,  H03F2200/426 ,  H03F2200/444 ,  H03F2200/451 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode.

Abstract translation: 形成栅电极，以便通过栅极绝缘膜将电极材料嵌入已形成为叠层化合物半导体的结构的电极用凹部中，并且还形成与电极的肖特基接触的场板电极 堆叠的化合物半导体的结构通过将电极材料嵌入到在层叠的化合物半导体的结构中形成的电极的凹部中而形成，使得场板电极直接与堆叠的化合物半导体的结构接触 至少在用于电极的凹槽的底面上。

公开(公告)号：US08658482B2

公开(公告)日：2014-02-25

申请号：US12926990

申请日：2010-12-22

Applicant: Toshihide Kikkawa

Inventor： Toshihide Kikkawa

IPC: H01L21/338

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract translation: 化合物半导体器件包括形成在SiC衬底10上的i-GaN缓冲层12; 形成在i-GaN缓冲层12上的n-AlGaN电子供给层16; 形成在n-AlGaN电子供给层16上的n-GaN帽层18; 形成在n-GaN覆盖层18上的源电极20和漏电极22; 形成在源电极20和漏电极22之间的n-GaN覆盖层18上的栅电极26; 形成在源电极20和漏电极22之间的n-GaN覆盖层18上的第一保护层24; 以及第二保护层30，该第二保护层30形成在栅电极26和漏电极22之间的第一保护层24中的开口28中，直到n-GaN覆盖层18，并且由与第一保护层不同的绝缘膜形成。

公开(公告)号：US20130083569A1

公开(公告)日：2013-04-04

申请号：US13557332

申请日：2012-07-25

Applicant: Yuichi Minoura ,  Naoya Okamoto ,  Toshihide Kikkawa ,  Kozo Makiyama ,  Toshihiro Ohki

Inventor： Yuichi Minoura ,  Naoya Okamoto ,  Toshihide Kikkawa ,  Kozo Makiyama ,  Toshihiro Ohki

IPC: H01L21/283 ,  H02M5/458 ,  H01L23/48 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66212 ,  H01L29/7787 ,  H01L29/872 ,  H02M1/4225 ,  H02M3/33569 ,  H02M2001/007 ,  Y02B70/126

Abstract: A passivation film is formed on a compound semiconductor layered structure, an electrode formation scheduled position for the passivation film is thinned by dry etching, a thinned portion of the passivation film is penetrated by wet etching to form an opening, and a gate electrode is formed on the passivation film so as to embed this opening by an electrode material.

Abstract translation: 在化合物半导体层状结构上形成钝化膜，通过干蚀刻使钝化膜的电极形成预定位置变薄，通过湿蚀刻渗透钝化膜的薄化部分以形成开口，形成栅电极 在钝化膜上，以便通过电极材料嵌入该开口。

公开(公告)号：US20130032818A1

公开(公告)日：2013-02-07

申请号：US13552894

申请日：2012-07-19

Applicant: Masato Nishimori ,  Toshihide Kikkawa

Inventor： Masato Nishimori ,  Toshihide Kikkawa

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/1075 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

Abstract: A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.

Abstract translation: 半导体器件包括设置在衬底上的缓冲层，设置在缓冲层上的高电阻层，高电阻层掺杂有用于实现高电阻的过渡金属，低电阻区是 设置在高电阻层的一部分上或高电阻层的一部分上，低电阻区域掺杂有用于实现低电阻的杂质元素，设置在包含低电阻的高电阻层上的电子迁移层 设置在电子行进层上的电子供给层，设置在电子供给层上的栅电极以及设置在电子供给层上的源电极和漏电极。

公开(公告)号：US08357602B2

公开(公告)日：2013-01-22

申请号：US12886822

申请日：2010-09-21

Applicant: Masahito Kanamura ,  Toshihide Kikkawa

Inventor： Masahito Kanamura ,  Toshihide Kikkawa

IPC: H01L21/3205 ,  H01L21/461

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.

Abstract translation: 在沟道层和电子给体层之间形成由i-AlN构成的中间层，在电子供体层中形成第一开口，在稍后将形成栅电极的位置，同时使用中间层作为 蚀刻停止器，通过使用热磷酸溶液的湿蚀刻，在中间层中形成第二开口以与第一开口位置对准，并且形成栅电极，使得其下部填充第一和第二 开口，同时将栅极绝缘膜放置在其间，并且使得其头部突出在盖结构的上方。

公开(公告)号：US20120211762A1

公开(公告)日：2012-08-23

申请号：US13334766

申请日：2011-12-22

Applicant: Tadahiro IMADA ,  Keishiro Okamoto ,  Nobuhiro Imaizumi ,  Toshihide Kikkawa

Inventor： Tadahiro IMADA ,  Keishiro Okamoto ,  Nobuhiro Imaizumi ,  Toshihide Kikkawa

IPC: H01L29/778 ,  H01L21/56 ,  H01L23/48 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L29/41766 ,  H01L29/66462 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206

Abstract: A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip.

Abstract translation: 半导体器件包括：具有电极的半导体芯片; 对应于电极的引线; 将电极耦合到引线的金属线; 覆盖金属线和电极之间的耦合部分的第一树脂部分和金属线与引线之间的耦合部分; 以及覆盖金属线，第一树脂部分和半导体芯片的第二树脂部分。

公开(公告)号：US20110089430A1

公开(公告)日：2011-04-21

申请号：US12926990

申请日：2010-12-22

Applicant: Toshihide Kikkawa

Inventor： Toshihide Kikkawa

IPC: H01L29/772

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

公开(公告)号：US07859020B2

公开(公告)日：2010-12-28

申请号：US12173392

申请日：2008-07-15

Applicant: Toshihide Kikkawa ,  Kenji Imanishi

Inventor： Toshihide Kikkawa ,  Kenji Imanishi

IPC: H01L31/072

CPC classification number: H03F1/0288 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/7787 ,  H03F2200/15 ,  H03F2200/451 ,  H03F2200/543

Abstract: A nitride semiconductor device includes a substrate, a stacked semiconductor structure formed over the substrate and including a electron channel layer of an undoped nitride semiconductor and an electron supplying layer of an n-type nitride semiconductor formed epitaxially over the electron channel layer, the n-type nitride semiconductor having an electron affinity smaller than an electron affinity of said undoped nitride semiconductor and a two-dimensional electron gas being formed in the electron channel layer along an interface to the electron supply layer, a gate electrode formed over the stacked semiconductor structure in correspondence to a channel region, and source and drain electrodes formed over the stacked semiconductor structure in ohmic contact therewith respectively at a first side and a second side of the gate electrode, the stacked semiconductor structure including, between the substrate and the electron channel layer, an n-type conductive layer and a barrier layer containing Al formed consecutively and epitaxially.

Abstract translation: 氮化物半导体器件包括衬底，在衬底上形成的堆叠半导体结构，并且包括在电子沟道层外部形成的非掺杂氮化物半导体的电子沟道层和n型氮化物半导体的电子供给层， 具有小于所述未掺杂的氮化物半导体的电子亲和力的电子亲和力的二次电子气体和沿着与电子供应层的界面在电子通道层中形成的二维电子气的氮化物半导体，形成在堆叠半导体结构上的栅电极 对应于沟道区，以及源极和漏极，其形成在层叠的半导体结构上，分别与栅电极的第一侧和第二侧欧姆接触，该层叠半导体结构包括在衬底和电子通道层之间， n型导电层和阻挡层 aining铝连续形成和外延形成。