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公开(公告)号：US5585659A
公开(公告)日：1996-12-17
申请号：US320690
申请日：1994-10-11
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/02 , H01L29/78 , H01L29/76
CPC分类号： H01L21/823842
摘要： A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.
摘要翻译： 一种用于制造半导体器件的方法，其中用于互补型场效应半导体器件的多晶硅栅极由同时掺杂到多晶硅沉积的杂质的多晶硅形成; 两个门具有双N + / P +多晶硅栅极结构，使得N沟道晶体管和P沟道晶体管形成为表面沟道型晶体管; 因此，进行关闭特性，短通道效应和阈值电压的可控性。 更具体地，在公共半导体衬底（1）上提供N沟道和P沟道MISFET。 采用N型杂质掺杂的N型多晶硅（9）作为N沟道MISFET的栅电极; 采用掺杂有P型杂质的P型多晶硅（8）作为P沟道MISFET的栅电极; 并且在各个多晶硅的部分之间设置防止杂质相互扩散的窄区域。
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公开(公告)号：US5382532A
公开(公告)日：1995-01-17
申请号：US946080
申请日：1992-09-16
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/02 , H01L29/78 , H01L21/265
CPC分类号： H01L21/823842
摘要： A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.
摘要翻译： 一种用于制造半导体器件的方法，其中用于互补型场效应半导体器件的多晶硅栅极由同时掺杂到多晶硅沉积的杂质的多晶硅形成; 两个门具有双N + / P +多晶硅栅极结构，使得N沟道晶体管和P沟道晶体管形成为表面沟道型晶体管; 因此，进行关闭特性，短通道效应和阈值电压的可控性。 更具体地，在公共半导体衬底（1）上提供N沟道和P沟道MISFET。 采用N型杂质掺杂的N型多晶硅（9）作为N沟道MISFET的栅电极; 采用掺杂有P型杂质的P型多晶硅（8）作为P沟道MISFET的栅电极; 并且在各个多晶硅的部分之间设置防止杂质相互扩散的窄区域。
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公开(公告)号：US5213991A
公开(公告)日：1993-05-25
申请号：US856801
申请日：1992-03-24
IPC分类号： H01L21/20 , H01L21/336 , H01L21/768 , H01L29/10 , H01L29/417 , H01L29/45 , H01L29/78
CPC分类号： H01L29/66651 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76877 , H01L29/1033 , H01L29/41725 , H01L29/456 , H01L29/78
摘要： In a method of making a MOSFET-type semiconductor device of this invention, a surface of a semiconductor substrate is covered in a predetermined pattern with an insulating layer comprising a silicon-nitride-containing film or with an insulating layer whose top surface and side surfaces bear a silicon-nitride-containing film, thereby forming on the semiconductor substrate a recess region at which the semiconductor substrate is exposed. An epitaxial silicon film and polycrystalline silicon film are formed simultaneously on the exposed semiconductor substrate and on the insulating film, respectively. A whole channel region and a part of source and drain diffused-layer regions are formed in the epitaxial silicon film, and source and drain diffused-layer regions are formed in the polycrystalline silicon film. A gate electrode of this MOSFET-type semiconductor device may be formed at the recess region by a self-align method.
摘要翻译： 在制造本发明的MOSFET型半导体器件的方法中，半导体衬底的表面以包含含氮化硅的膜的绝缘层或具有绝缘层的预定图案被覆盖，所述绝缘层的顶表面和侧表面 承载含氮化硅的膜，从而在半导体衬底上形成露出半导体衬底的凹部区域。 外延硅膜和多晶硅膜分别同时形成在暴露的半导体衬底和绝缘膜上。 在外延硅膜中形成整个沟道区域和一部分源极和漏极扩散层区域，并且在多晶硅膜中形成源极和漏极扩散层区域。 该MOSFET型半导体器件的栅极可以通过自对准方法在凹陷区域形成。
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公开(公告)号：US20130337125A1
公开(公告)日：2013-12-19
申请号：US13523804
申请日：2012-06-14
申请人： Toshio Kobayashi
发明人： Toshio Kobayashi
摘要： In a raw material preparing step, a rice powder as a primary raw material powder is added with a water to prepare a mixed raw material. In a kneading step, the mixed raw material is kneaded to form a kneaded substance. In a pressing/extending step, the kneaded substance is pressed and extended to form noodle dough sheet. In a slitting step, the noodle dough sheet is slit into predetermined noodle strand shape to obtain a continuous noodle strand However, these steps maintain a non-alpha state of the rice powder component In a packaging step, a unit-length noodle strand is accommodated in a pouch-like heat-resistant packaging container and hermetically sealed to obtain a packaged unit-length noodle strand, while maintaining a non-alpha state of the rice powder component in the noodle strand.
摘要翻译： 在原料制备工序中，将作为主要原料粉末的米粉加入水中以制备混合原料。 在捏合步骤中，将混合的原料捏合以形成捏合物。 在压延/延伸步骤中，将捏合的物质压制并延伸以形成面条面片。 在切割步骤中，将面条片切成预定的面条形状以获得连续的面条。然而，这些步骤保持米粉成分的非α状态在包装步骤中，容纳单位面条 在袋状耐热包装容器中进行气密密封以获得包装的单位长度的面条，同时保持面粉条中的米粉成分的非α状态。
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5.发明申请公开(公告)号：US20130313267A1
公开(公告)日：2013-11-28
申请号：US13983507
申请日：2012-08-31
申请人： Yoshimasa Horio , Shinya Nagahata , Toshio Kobayashi , Tarou Yamaguchi , Shuhei Sugimoto , Kazuya Nakanishi , Junichi Kurita , Hiroki Hamano , Shinya Kojima , Noriyuki Miyaji
发明人： Yoshimasa Horio , Shinya Nagahata , Toshio Kobayashi , Tarou Yamaguchi , Shuhei Sugimoto , Kazuya Nakanishi , Junichi Kurita , Hiroki Hamano , Shinya Kojima , Noriyuki Miyaji
IPC分类号： F25D11/00
CPC分类号： F25D11/00 , F25D23/06 , F25D2201/14
摘要： The present invention provides a refrigerator with improved refrigerator box strength and high heat insulating performance, which is configured such that external deformation due to entry of air into a vacuum heat insulating material, the entry of air being caused by aging degradation, is prevented. The present invention includes: a heat-insulated box including an inner casing and an outer casing, in which space between the inner casing and the outer casing is filled with a foamed heat insulating material; and a vacuum heat insulating material disposed in at least a side wall of the heat-insulated box together with the foamed heat insulating material, the vacuum heat insulating material including an outer skin material, the outer skin material including at least a core material and being decompression-sealed. The vacuum heat insulating material includes a gas adsorbent. Since the vacuum heat insulating material including the gas adsorbent is included in the side wall, which tends to be greatly distorted among the heat insulating walls of the refrigerator, the rigidity of the side wall is improved and aging degradation of the vacuum heat insulating material is suppressed. As a result, the rigidity of the heat-insulated box can be maintained for a long term, and external deformation of the outer casing of the body can be prevented.
摘要翻译： 本发明提供了一种具有改善的冰箱箱强度和高绝热性能的冰箱，其被构造成使得由于空气进入真空绝热材料而导致的外部变形，由老化劣化引起的空气进入。 本发明包括：包括内壳和外壳的绝热箱，其中内壳和外壳之间的空间填充有泡沫绝热材料; 以及设置在所述隔热箱的至少侧壁中的所述真空绝热材料与所述发泡绝热材料一起，所述真空绝热材料包括外皮材料，所述外皮材料至少包括芯材，并且是 减压密封。 真空绝热材料包括气体吸附剂。 由于包括气体吸附剂的真空隔热材料包括在侧壁中，在冰箱的绝热壁之间容易发生大的变形，所以侧壁的刚性提高，真空隔热材料的老化劣化是 被压制 结果，可以长期保持隔热箱的刚性，并且可以防止身体的外壳的外部变形。
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公开(公告)号：US20120153507A1
公开(公告)日：2012-06-21
申请号：US13331121
申请日：2011-12-20
申请人： Syota MIKI , Takaharu Yamano , Toshio Kobayashi
发明人： Syota MIKI , Takaharu Yamano , Toshio Kobayashi
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/19 , H01L2224/12105 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer.
摘要翻译： 一种方法包括在支撑体的一个表面上设置具有形成在电路形成表面上的电极焊盘的半导体芯片，使得电极焊盘与支撑体的一个表面接触，在支撑体的一个表面上形成第一绝缘层， 第一绝缘层至少覆盖半导体芯片的侧表面，去除支撑并在电极焊盘上形成互连端子，在半导体芯片的电路形成表面和第一绝缘层上形成第二绝缘层，使得 所述第二绝缘层覆盖所述互连端子，将所述互连端子的端部从所述第二绝缘层的顶表面露出，并且形成与所述互连端子的端部电连接的布线图案， 第二绝缘层。
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公开(公告)号：US07807510B2
公开(公告)日：2010-10-05
申请号：US12123744
申请日：2008-05-20
申请人： Toshio Kobayashi
发明人： Toshio Kobayashi
CPC分类号： H05K1/144 , H01L21/565 , H01L23/3128 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H05K3/3436 , H05K2201/10234 , H05K2201/10977 , H05K2203/1322 , H01L2924/00012 , H01L2924/00
摘要： There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.
摘要翻译： 提供了通过线14将芯片部件13连接到第一基板10的步骤，在第二基板20上提供电极21，将电极21附接到第一基板10，模制工具30具有对应形成的突出部分31 涉及第一基板10的凸块连接焊盘12的阵列和与安装芯片部件13的区域对应地形成的空腔32，由此形成用于密封芯片部件13和导线14的第一密封树脂34， 通过焊料将电极21接合到凸块连接焊盘12，从而将第一基板10接合到第二基板20，并且将第二填充树脂40填充在第一基板10和第二基板20之间的间隙部分中。
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公开(公告)号：US07159303B2
公开(公告)日：2007-01-09
申请号：US11371244
申请日：2006-03-09
申请人： Ryoichi Nakatani , Masahiro Kitada , Naoki Koyama , Isamu Yuito , Hisashi Takano , Eijin Moriwaki , Mikio Suzuki , Masaaki Futamoto , Fumio Kugiya , Yoshibumi Matsuda , Kazuo Shiiki , Yoshinori Miyamura , Kyo Akagi , Takeshi Nakao , Hirotsugu Fukuoka , Takayuki Munemoto , Tokuho Takagaki , Toshio Kobayashi , Hideo Tanabe , Noboru Shimizu
发明人： Ryoichi Nakatani , Masahiro Kitada , Naoki Koyama , Isamu Yuito , Hisashi Takano , Eijin Moriwaki , Mikio Suzuki , Masaaki Futamoto , Fumio Kugiya , Yoshibumi Matsuda , Kazuo Shiiki , Yoshinori Miyamura , Kyo Akagi , Takeshi Nakao , Hirotsugu Fukuoka , Takayuki Munemoto , Tokuho Takagaki , Toshio Kobayashi , Hideo Tanabe , Noboru Shimizu
IPC分类号： G11B5/127
CPC分类号： G11B5/398 , B82Y10/00 , B82Y25/00 , G01R33/093 , G11B5/3903 , G11B5/3909 , G11B5/3929 , G11B5/3967 , G11B2005/0002 , G11B2005/0016 , G11B2005/3996 , H01F10/324 , H01F10/3254 , H01F10/3268 , H01L43/08 , Y10T29/49032 , Y10T29/49043 , Y10T29/49044 , Y10T29/49155
摘要： The magnetoresistance effect element is of a multilayered structure having at least magnetic layers and an intermediate layer of an insulating material, a semiconductor or an antiferromagnetic material against the magnetic layers, and the magnetoresistance effect element has terminals formed at least on the opposite magnetic layers, respectively, so that a current flows in the intermediate layer. The film surfaces of all the magnetic layers constituting the magnetoresistance effect element are opposed substantially at right angles to the recording surface of a magnetic recording medium. Therefore, the area of the magnetic layers facing the recording surface of the magnetic recording medium can be extremely reduced, and thus the magnetic field from a very narrow region of the high-density recorded magnetic recording medium can be detected by the current which has a tunneling characteristic and passes through the intermediate layer.
摘要翻译： 磁阻效应元件是至少具有磁性层和抵抗磁性层的绝缘材料，半导体或反铁磁材料的中间层的多层结构，并且磁阻效应元件至少在相对的磁性层上形成端子， 使得电流在中间层中流动。 构成磁阻效应元件的所有磁性层的膜表面基本上与磁记录介质的记录表面成直角相对。 因此，能够极大地降低与磁记录介质的记录面对置的磁性层的面积，因此能够通过电流检测来自高密度记录磁记录介质的非常窄的区域的磁场 穿透特性，穿过中间层。
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9.发明授权公开(公告)号：US07023061B2
公开(公告)日：2006-04-04
申请号：US11072505
申请日：2005-03-07
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译： 一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复 在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。
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10.发明授权公开(公告)号：US06949788B2
公开(公告)日：2005-09-27
申请号：US09735903
申请日：2000-12-14
申请人： Ichiro Fujiwara , Toshio Kobayashi
发明人： Ichiro Fujiwara , Toshio Kobayashi
IPC分类号： H01L21/8247 , G11C11/40 , G11C16/04 , H01L21/28 , H01L21/318 , H01L21/336 , H01L21/82 , H01L27/105 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792 , H01L31/062
CPC分类号： G11C16/0491 , G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in the vicinity of a surface of a substrate, first and second impurity regions, acting as a source and a drain in operation, formed in the vicinity of the surface of the substrate sandwiching the channel forming region between them, a gate insulating film stacked on the channel forming region and having a plurality of films, and a charge storing means that is formed in the gate insulating film dispersed in the plane facing the channel forming region. A bottom insulating film includes a dielectric film that exhibits a FN type electroconductivity and makes the energy barrier between the bottom insulating film and the substrate lower than that between silicon dioxide and silicon.
摘要翻译： 具有通过热电子注入提高效率的MONOS型存储单元和改进的结垢特性的非易失性半导体存储器件包括在衬底表面附近的沟道形成区域，作为源极和漏极的第一和第二杂质区域 形成在夹在其间的沟道形成区域的基板的表面附近，堆叠在沟道形成区上并具有多个膜的栅极绝缘膜，以及形成在栅极绝缘膜中的电荷存储装置 分散在面向通道形成区域的平面中。 底部绝缘膜包括具有FN型导电性并使底部绝缘膜和衬底之间的能量阻挡比二氧化硅和硅之间的能量阻挡的电介质膜。
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