公开(公告)号：US5328810A

公开(公告)日：1994-07-12

申请号：US981976

申请日：1992-11-25

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  David A. Cathey

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  David A. Cathey

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  G03C5/00

CPC分类号： H01L21/3088 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  Y10S148/106

摘要： The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space width which is also approximately equal to F. From this primary mask, a set of expendable mandrel strips is created either directly or indirectly. The set of mandrel strips may be characterized as a pattern of parallel strips, each having a feature width of F/2, and with neighboring strips being spaced from one another by a space width equal to 3/2F. A conformal stringer layer is then deposited. The stringer layer material is selected such that it may be etched with a high degree of selectivity with regard to both the mandrel strips and an underlying layer which will ultimately be patterned using a resultant, reduced-pitch mask. The stringer layer is then anisotropically etched to the point where the top of each mandrel strip is exposed. The mandrel strips are then removed with an appropriate etch. A pattern of stringer strips remains which can then be used as a half-pitch mask to pattern the underlying layer. This process may also be repeated, starting with the half-pitch mask and creating a quarter-pitch mask, etc. As can be seen, this technique permits a reduction in the minimum pitch of the primary mask by a factor of 2.sup.-N (where N is an integer 1, 2, 3, . . . ).

摘要翻译： 该过程从初始掩模开始，其可以被表征为具有基本垂直边缘的平行的光致抗蚀剂条带的图案，每个具有最小特征宽度F，并且与相邻条带分开最小空间宽度，其最大空间宽度也近似等于 F.从这个主要面罩，直接或间接地创建一组消耗性的芯棒条。 芯棒条的组可以被表征为平行条带的图案，每个条带具有F / 2的特征宽度，并且相邻条带彼此间隔开等于3 / 2F的空间宽度。 然后沉积保形纵梁层。 选择桁条层材料，使得可以以相对于芯棒条和下一层的高度选择性蚀刻，其将最终使用所得到的减少节距的掩模进行图案化。 然后将纵梁层各向异性地蚀刻到每个芯棒条的顶部暴露的点。 然后用适当的蚀刻去除心轴条。 留下一条桁条条纹，然后可以将其作为半间距掩模用于对下层进行图案化。 该过程也可以重复，从半间距掩模开始并产生四分之一间距掩模等。可以看出，该技术允许将初级掩模的最小间距减小2-N倍（ 其中N是整数1,2,3，...）。

公开(公告)号：US5581104A

公开(公告)日：1996-12-03

申请号：US425678

申请日：1995-04-18

申请人： Tyler A. Lowrey ,  Randal W. Chance

发明人： Tyler A. Lowrey ,  Randal W. Chance

IPC分类号： G06F15/78 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L29/0626 ,  H01L27/0251 ,  H01L29/861 ,  H01L2924/0002

摘要： A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt excess current away from sensitive regions with even current distribution for minimal damage. In order to improve the ESD immunity of the positive going ESD with respect to V.sub.SS, the reverse bias breakdowns of the diode and of the transistor's functioning as a collector/base diode are reduced. This circuit provides a simple low cost approach for improving ESD protection, in a process which fits into most standard Cmos process flows with few or no added process steps.

摘要翻译： 在集成电路的输入焊盘上设置双极晶体管和双极二极管，以便分流由静电放电（ESD）引起的电涌。 该方法利用双极和二极管钳位，具有从集电极到基极的优化的反向偏置击穿，以将过电流从具有均匀电流分布的敏感区域分流，以实现最小的损坏。 为了提高正向ESD相对于VSS的ESD抗扰性，二极管和作为集电极/基极二极管的晶体管的反向偏压故障降低。 该电路提供了一种简单的低成本方法来改善ESD保护，在一个适合大多数标准Cmos工艺流程的过程中，几乎没有或没有附加的工艺步骤。

公开(公告)号：US4957878A

公开(公告)日：1990-09-18

申请号：US189411

申请日：1988-05-02

申请人： Tyler A. Lowrey ,  Randal W. Chance

发明人： Tyler A. Lowrey ,  Randal W. Chance

IPC分类号： H01L21/8242 ,  H01L27/105

CPC分类号： H01L27/10844 ,  H01L27/105

摘要： A dynamic randon access memory (DRAM) is formed in a series of masking steps, during which a first layer of polysilicon is anisotropically etched. After the anisotropic etch, junctions are added to the polysilicon through doping techniques. A second layer of polysilicon is then deposited and is isotropically etched. By the sequence, critical dimensions are established at preliminary mask layers and subsequent layers do not require the high degree of criticality of dimension.

摘要翻译： 在一系列掩蔽步骤中形成动态随机存取存储器（DRAM），在此期间第一层多晶硅被各向异性蚀刻。 在各向异性蚀刻之后，通过掺杂技术将结结添加到多晶硅中。 然后沉积第二层多晶硅并进行各向同性蚀刻。 按照顺序，临界尺寸在初步掩模层上建立，随后的层不需要高度的尺寸临界度。

公开(公告)号：US5208125A

公开(公告)日：1993-05-04

申请号：US738063

申请日：1991-07-30

申请人： Tyler A. Lowrey ,  Randal W. Chance

发明人： Tyler A. Lowrey ,  Randal W. Chance

IPC分类号： G03F1/28 ,  G03F1/30

CPC分类号： G03F1/28 ,  G03F1/30

摘要： A method of fabricating a phase shifting reticle that can be used as a mask in photolithographic processes such as semiconductor wafer patterning. A transparent quartz substrate is subjected to high voltage ion bombardment to produce patterns of ion implant areas on the substrate. By carefully selecting the dopants for ion implantation and closely controlling the implantation process, areas on the substrate are produced having an absorption property for forming an opaque light blocking area or indexes of refraction different than the quartz substrate and selected to achieve a 0.degree. to 180.degree. phase shift area. This produces a repetitive pattern of alternating light transmission openings and phase shifters having opaque light blockers on either side. Additionally, tapered phase shifters may be implanted into the substrate to extend from a 180.degree. phase shift area into a light transmission opening at a 0.degree. phase shift.

摘要翻译： 一种制造可用作诸如半导体晶片图案化的光刻工艺中的掩模的相移掩模版的方法。 对透明石英衬底进行高压离子轰击，以在衬底上产生离子注入区域的图案。 通过仔细选择用于离子注入的掺杂剂并且密切地控制注入工艺，产生具有用于形成不同于石英衬底的不透明遮光面积或折射率的吸收性能的衬底上的区域，并选择实现0°至180° DEG相移区域。 这产生交替的光传输开口的重复图案和在任一侧上具有不透明光阻挡器的移相器。 此外，锥形移相器可以注入到基板中，从180度相移区域延伸到0°相移的透光开口。

公开(公告)号：US5013680A

公开(公告)日：1991-05-07

申请号：US555980

申请日：1990-07-18

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/334 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L21/033 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/768 ,  H01L29/66181 ,  H01L29/66666 ,  Y10S438/947

摘要： A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.

摘要翻译： 一种用于创建DRAM阵列的方法，其具有仅使用五个光掩模步骤超越所使用的光刻工艺的分辨率极限的特征宽度。 该方法包括以下步骤：产生半间距硬材料掩模，其用于蚀刻硅衬底中的一系列等间隔隔开的隔离沟槽; 用绝缘材料填充隔离沟; 由宽度为1-1 / 2F的条形成的宽度为1 / 2F的间隔的用于蚀刻存储沟槽的矩阵的硬质材料掩模的形成; 在存储沟槽壁中倾斜注入N型杂质; 另一种各向异性蚀刻来加深存储沟槽; 沉积电容器电介质层; 保护性多晶硅层在电介质层的顶部上沉积; 通过进一步的各向异性蚀刻在每个存储沟槽的底部去除电介质层和保护性多晶硅层; 用原位掺杂多晶硅填充存储沟槽; 平坦化到底层水平; 在每个存储沟槽的相对侧上形成存取栅极，除了通过各向异性蚀刻已经沉积在垂直于隔离沟槽的氧化物 - 硅台面顶部上的共形导电层来互连阵列列内的栅极的字线之外，并且是 在存储沟槽的行之间居中，使用由具有最小特征和空间宽度放置的一系列平行条组成的光刻胶掩模，然后将等离子体蚀刻到3 / 4F，利用蚀刻产生氧化物 - 硅台面; 用N型植入物创建源和排水沟; 并各向异性地蚀刻金属层以沿着氧化物台面的侧壁产生位线。

公开(公告)号：US5177027A

公开(公告)日：1993-01-05

申请号：US569353

申请日：1990-08-17

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/423

CPC分类号： H01L29/66477 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2815 ,  H01L21/31662 ,  H01L21/76237 ,  H01L27/10873 ,  H01L29/66666 ,  H01L29/4236

摘要： A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gate oxide layer on the substrate and vertical sidewalls of the mesa; blanket deposition of a gate layer (typically polysilicon); anisotropically etching the gate layer to expose the upper surface of the mesa and leave a stringer gate around the circumference thereof; and doping the upper surface of the mesa and regions of the substrate peripheral to the circumferential polysilicon stringer to create source and drain regions. The standard process provides device density approximately double that of standard FET fabrication processes. Density can be increased even further by increasing the number of silicon mesas with a minimum pitch distance. This may be accomplished by employing the reduced-pitch masking technique disclosed in a copending U.S. patent application. Multiple transistors may be created on a single mesa by creating isolation regions within the mesa. The circumferential gate may be severed so as to provide a pair of gate inputs for transistors created on a single mesa. Enhancements common to conventional MOSFETS, such as lightly-doped source and drains, halos, etc., may be utilized for the new MOSFET process.

摘要翻译： 在硅台面的或多或少垂直边缘上制造具有间隔物形栅极和直角沟道路径的MOS场效应晶体管的工艺。 该方法包括以下步骤：在平面硅衬底上产生凸起区域（台面）; 在基板上形成栅极氧化物层和台面的垂直侧壁; 栅极层（通常为多晶硅）的覆盖沉积; 各向异性地蚀刻栅极层以暴露台面的上表面并且围绕其周边留下纵梁; 并且将周向多晶硅桁条外围的台面的上表面和基板的区域掺杂以产生源区和漏区。 标准工艺提供的器件密度约为标准FET制造工艺的两倍。 通过增加具有最小间距距离的硅台面的数量，可进一步增加密度。 这可以通过采用共同未决的美国专利申请中公开的减少节距掩蔽技术来实现。 可以通过在台面内创建隔离区域，在单个台面上创建多个晶体管。 可以切断周向栅极，以便为在单个台面上产生的晶体管提供一对栅极输入。 对于新的MOSFET工艺，可以使用传统MOSFETs通用的增强功能，例如轻掺杂源极和漏极，卤素等。

公开(公告)号：US5032530A

公开(公告)日：1991-07-16

申请号：US427639

申请日：1989-10-27

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823807

摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology. Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

摘要翻译： 一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化。 改进的过程的目的是通过显着减少制造晶体管所需的光掩模步骤的数量来降低成本并提高CMOS器件的可靠性和可制造性。 通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。 从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。 与传统工艺技术相比，改进的CMOS工艺提供了以下优点。 不需要对N沟道器件使用屏蔽的高能穿孔植入物; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

公开(公告)号：US5087951A

公开(公告)日：1992-02-11

申请号：US713535

申请日：1991-06-06

申请人： Randal W. Chance ,  Tyler A. Lowrey

发明人： Randal W. Chance ,  Tyler A. Lowrey

IPC分类号： H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A dymanic random access memory device is constructed in which a first layer of semiconductive material is used to form series of transistors, using buried contacts on a silicon substrate. A dielectric is formed over the surface, and memory cells include a second layer of semiconductive material which is deposited over a dielectric. The active regions of the DRAM form a "dogbone" pattern, in which active regions exhibit elongate shapes in which each end of the elongate shape is wider than a center leg, and adjacent "dogbone" shapes are nested to form a compact pattern.

摘要翻译： 构建了一种二进制随机存取存储器件，其中使用半导体材料的第一层来形成串联的晶体管，使用硅衬底上的掩埋触点。 在表面上形成电介质，并且存储单元包括沉积在电介质上的第二半导体材料层。 DRAM的有源区域形成“狗骨”图案，其中活动区域呈现细长形状，其中细长形状的每个端部比中心腿宽，并且相邻的“狗骨”形状被嵌套以形成紧凑图案。

公开(公告)号：US20100092890A1

公开(公告)日：2010-04-15

申请号：US12636317

申请日：2009-12-11

申请人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： G03F7/20

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

摘要翻译： 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。

公开(公告)号：US07655387B2

公开(公告)日：2010-02-02

申请号：US10934317

申请日：2004-09-02

申请人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： G03F7/00

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

摘要翻译： 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。