公开(公告)号：US20060110903A1

公开(公告)日：2006-05-25

申请号：US11273261

申请日：2005-11-15

申请人： Uwe Schroder ,  Jochen Schacht

发明人： Uwe Schroder ,  Jochen Schacht

IPC分类号： H01L21/44

CPC分类号： H01L21/76816

摘要： In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing a regular pattern of contact structures with a period which corresponds to the order of magnitude of twice the edge length of the contact hole, and with the second mask containing a pattern with a structure which surrounds at least the contact hole area, and thus covers it.

摘要翻译： 为了在基板上的层中形成接触，特别是在半导体部件中的逻辑电路中的接触，掩模层被构造为用与两个掩模一起曝光的光致抗蚀剂层蚀刻接触孔， 第一掩模包含具有对应于接触孔的边缘长度的两倍的数量级的周期的接触结构的规则图案，并且第二掩模包含具有至少围绕接触孔区域的结构的图案，以及 从而覆盖它。

公开(公告)号：US20050277295A1

公开(公告)日：2005-12-15

申请号：US11147892

申请日：2005-06-08

申请人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroder

发明人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroder

IPC分类号： C23C14/04 ,  C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  H01L21/20 ,  H01L21/283 ,  H01L21/285 ,  H01L21/31 ,  H01L21/314 ,  H01L21/44 ,  H01L21/469 ,  H01L21/66 ,  H01L21/762 ,  H01L21/768

CPC分类号： C23C16/0281 ,  C23C14/046 ,  C23C16/045 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/76877 ,  H01L22/26

摘要： The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).

摘要翻译： 本发明提供一种用于图案化衬底表面的涂覆方法，其中提供衬底（101），该衬底具有在衬底图案化区域（102）中被图案化并具有一个或多个沟槽（106）的表面（105） 将其填充到预定的填充高度（205），将催化剂层（201）引入要填充的沟槽（106）中，在沟槽（106）中催化沉积反应层（202），其中 要填充的催化沉积反应层（202）在要填充的沟槽（106）中致密化，并且重复引入催化剂层（201）和催化沉积反应层（202） 直到要填充的沟槽（106）已经被填充到预定填充高度（205）。

公开(公告)号：US20060275981A1

公开(公告)日：2006-12-07

申请号：US11442602

申请日：2006-05-30

申请人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

发明人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。

公开(公告)号：US20050164464A1

公开(公告)日：2005-07-28

申请号：US11042326

申请日：2005-01-26

申请人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schroder

发明人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schroder

IPC分类号： C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/314 ,  H01L21/334 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20 ,  H01L21/76

CPC分类号： C23C16/045 ,  C23C16/45525 ,  H01L21/3065 ,  H01L21/3141 ,  H01L27/10808 ,  H01L27/10829 ,  H01L27/10852 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.

摘要翻译： 在通常为半导体晶片的衬底（其形式为浮雕形式的衬底表面）上，使用沉积工艺来提供在相对于衬底表面垂直或倾斜的工艺表面上的覆盖层 。 通过限制至少一种前体材料的工艺量和/或通过临时限制沉积工艺，将覆盖层图案化成相对于衬底表面垂直的方向，并形成为后续工艺的功能层或掩模 脚步。

公开(公告)号：US07709359B2

公开(公告)日：2010-05-04

申请号：US11850218

申请日：2007-09-05

申请人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

发明人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

IPC分类号： H01L29/72

CPC分类号： H01L21/28291 ,  H01L27/10873 ,  H01L28/40 ,  H01L28/91 ,  H01L29/513 ,  H01L29/78

摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.

摘要翻译： 公开了一种在衬底上制造具有电介质层的集成电路的方法。 一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

公开(公告)号：US20090057737A1

公开(公告)日：2009-03-05

申请号：US11850218

申请日：2007-09-05

申请人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

发明人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

IPC分类号： H01L29/76 ,  H01L21/00

CPC分类号： H01L21/28291 ,  H01L27/10873 ,  H01L28/40 ,  H01L28/91 ,  H01L29/513 ,  H01L29/78

摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.

摘要翻译： 公开了一种在衬底上制造具有电介质层的集成电路的方法。 一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

公开(公告)号：US20070210367A1

公开(公告)日：2007-09-13

申请号：US11606381

申请日：2006-11-30

申请人： Henry Bernhardt ,  Thomas Hecht ,  Michael Stadtmueller ,  Christian Kapteyn ,  Uwe Schroder ,  Yeong-Kwan Kim ,  Andreas Spitzer

发明人： Henry Bernhardt ,  Thomas Hecht ,  Michael Stadtmueller ,  Christian Kapteyn ,  Uwe Schroder ,  Yeong-Kwan Kim ,  Andreas Spitzer

IPC分类号： H01L29/94

CPC分类号： H01L28/40 ,  H01L27/10861

摘要： A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.

摘要翻译： 存储电容器包括布置在第一电极层和第二电极层之间的第一电极层，第二电极层和介电中间层。 电介质中间层包含高k电介质和至少一种含硅组分。

公开(公告)号：US20050181557A1

公开(公告)日：2005-08-18

申请号：US11040091

申请日：2005-01-24

申请人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schroder ,  Matthias Goldbach

发明人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schroder ,  Matthias Goldbach

IPC分类号： H01L21/20 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31616 ,  H01L29/66181

摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

公开(公告)号：US20050106476A1

公开(公告)日：2005-05-19

申请号：US10965693

申请日：2004-10-14

申请人： Jens Hassmann ,  Johannes Kowalewski ,  Gerhard Kunkel ,  Thorsten Schedel ,  Uwe Schroder ,  Ina Voigt

发明人： Jens Hassmann ,  Johannes Kowalewski ,  Gerhard Kunkel ,  Thorsten Schedel ,  Uwe Schroder ,  Ina Voigt

IPC分类号： G03F7/20 ,  G03F9/00 ,  G03B27/54 ,  G03C5/00 ,  G03F1/08

CPC分类号： G03F7/70433

摘要： An item of information about the respective positions (501, 502, 601, 602) of at least two structure elements (50, 60) on a mask is provided. The displacement of the positional positions during the imaging by the lens system of the exposure apparatus, the displacement being governed by lens aberration, is measured and correction values (540, 640) are determined for each of the structure elements. Using the correction values (540, 640) the positions (501, 502, 601, 602) are changed in order to form new positions (505, 506, 605, 606) of the structure elements (50, 60) in such a way that the aberration effects can be compensated for. A mask (40) adapted to the exposure apparatus is exposed with the structures at the changed positions. The variation in the positional accuracies and the structure width distributions which is governed by the aberration of lenses is advantageously reduced.

摘要翻译： 提供关于掩模上的至少两个结构元件（50,60）的相应位置（501,502,601,602）的信息的项目。 测量由曝光装置的透镜系统进行的成像期间的位置位置的位移，由透镜像差控制的位移，并为每个结构元件确定校正值（540,640）。 使用校正值（540,640），改变位置（501,502,601,602），以便以这种方式形成结构元件（50,60）的新位置（505,506,605,606） 可以补偿像差效应。 适用于曝光装置的掩模（40）以改变的位置的结构曝光。 有利地减少了由透镜的像差所决定的位置精度和结构宽度分布的变化。

公开(公告)号：US20050003642A1

公开(公告)日：2005-01-06

申请号：US10835259

申请日：2004-04-30

申请人： Thomas Hecht ,  Uwe Schroder ,  Ulrich Mantz ,  Stefan Jakschik ,  Andreas Orth

发明人： Thomas Hecht ,  Uwe Schroder ,  Ulrich Mantz ,  Stefan Jakschik ,  Andreas Orth

IPC分类号： G01B11/22 ,  G01J3/453 ,  G01N21/21 ,  H01L21/337

CPC分类号： G01N21/211 ,  G01B11/22 ,  G01J3/453

摘要： The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.

摘要翻译： 本发明涉及一种用于确定半导体晶片中的掩埋结构的深度的方法。 根据本发明，当半导体晶片在红外范围内被电磁辐射照射时，由掩埋结构引起的半导体晶片的层行为，并且由于与所使用的辐射相比显着更长的辐射波长而产生 掩埋结构的横向尺寸用于通过光谱测量和/或椭偏方法确定掩埋结构的深度。