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1.发明授权Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material 有权制造包括由高介电常数材料制成的栅极电介质的半导体器件的方法公开(公告)号：US07129563B2
公开(公告)日：2006-10-31
申请号：US10815473
申请日：2004-04-01
IPC分类号： H01L31/0256
CPC分类号： H01L21/28185 , H01L21/2807 , H01L21/28194 , H01L29/4925 , H01L29/51 , H01L29/517
摘要： A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1−xGex, where 0.5
摘要翻译： 用于制造具有由高k材料制成的栅极电介质的半导体器件的工艺和器件包括直接在栅极电介质上沉积第一层Si 1-x Ge的步骤， 在基本上低于通过热化学气相沉积（CVD）沉积多晶硅的温度的温度下，其中0.5
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公开(公告)号：US07381267B2
公开(公告)日：2008-06-03
申请号：US10816214
申请日：2004-04-01
CPC分类号： C30B25/18 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02639
摘要： A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.
摘要翻译： 通过外延生长单晶半导体晶片上的杂原子单晶半导体层的方法，所述层和晶片的晶格不同，包括在外延前在晶片表面形成至少 一个有用区域周围的不连续环。
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公开(公告)号：US20070248818A1
公开(公告)日：2007-10-25
申请号：US10583235
申请日：2004-12-16
IPC分类号： B32B19/00
CPC分类号： H01L29/04 , B82Y10/00 , G02B1/02 , G02B5/18 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L31/0352 , Y10T428/29
摘要： The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism
摘要翻译： 本发明涉及包括第二半导体材料的单晶纳米结构的第一半导体材料的单晶层，该纳米结构分布在具有中心的四边形棱镜的规则晶体网络中
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公开(公告)号：US20110108801A1
公开(公告)日：2011-05-12
申请号：US13004384
申请日：2011-01-11
CPC分类号： H01L29/04 , B82Y10/00 , G02B1/02 , G02B5/18 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L31/0352 , Y10T428/29
摘要： A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
摘要翻译： 包括第二半导体材料的单晶纳米结构的第一半导体材料的单晶层，所述纳米结构分布在具有中心四棱柱的规则晶体网络中。
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公开(公告)号：US06596555B2
公开(公告)日：2003-07-22
申请号：US09921642
申请日：2001-08-03
IPC分类号： H01L2120
CPC分类号： H01L33/06 , B82Y10/00 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L21/0262 , H01L29/127 , H01L33/0054 , Y10S438/962 , Y10S977/721 , Y10S977/891
摘要： A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.
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公开(公告)号：US06399502B1
公开(公告)日：2002-06-04
申请号：US09540188
申请日：2000-03-31
IPC分类号： H01L2100
CPC分类号： H01L31/1812 , B82Y10/00 , B82Y20/00 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/32115 , H01L29/125 , H01L29/165 , H01L31/035254 , H01L33/24 , H01L33/34 , H01S5/0207 , H01S5/021 , H01S5/2234 , H01S5/3224 , Y02E10/50
摘要： The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0
摘要翻译： 该方法包括：在半导体衬底（2）中蚀刻具有预定宽度和深度的至少一个沟槽（3）; 在衬底和沟槽中沉积Si1-xGex（0
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公开(公告)号：US08263965B2
公开(公告)日：2012-09-11
申请号：US13004384
申请日：2011-01-11
IPC分类号： H01L29/12
CPC分类号： H01L29/04 , B82Y10/00 , G02B1/02 , G02B5/18 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L31/0352 , Y10T428/29
摘要： A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
摘要翻译： 包括第二半导体材料的单晶纳米结构的第一半导体材料的单晶层，所述纳米结构分布在具有中心四棱柱的规则晶体网络中。
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公开(公告)号：US06690027B1
公开(公告)日：2004-02-10
申请号：US10048719
申请日：2002-06-13
IPC分类号： H01L2706
CPC分类号： H01L33/34 , B82Y10/00 , B82Y20/00 , H01L21/30604 , H01L29/127 , H01L29/151 , H01S5/3227 , H01S5/3412
摘要： A method for forming on a Ge or Si monocrystalline substrate successive Si/Ge, Si/SiGe, or Si/SiGe/Ge layers for a Ge substrate and inversely for a Si substrate is described. Electrochemical treatment of the stack of layers to make the layers porous and form therein residual crystallites is also described. The invention may be used to provide devices having layers of planes of quantum drops.
摘要翻译： 描述了在Ge或Si单晶衬底上形成用于Ge衬底的连续Si / Ge，Si / SiGe或Si / SiGe / Ge层并且反向用于Si衬底的方法。 还描述了层叠层的电化学处理以使层多孔并在其中形成残余微晶。 本发明可以用于提供具有量子滴的平面层的器件。
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9.发明授权公开(公告)号：US06429098B1
公开(公告)日：2002-08-06
申请号：US09659913
申请日：2000-09-11
IPC分类号： H01L2120
CPC分类号： C30B25/02 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： The process consists in depositing, by chemical vapour deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450° C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.
摘要翻译： 该方法包括通过使用硅和锗前体气体的混合物的化学气相沉积，通过降低或增加800-450℃范围内的温度在锗或硅衬底上沉积硅或锗的单晶层。 并且同时通过分别在前体气体混合物中增加0至100％的Si / Ge或Ge / Si重量比。
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10.发明授权Process for nitriding the gate oxide layer of a semiconductor device and device obtained 失效用于氮化半导体器件的栅极氧化物层的工艺和所获得的器件公开(公告)号：US06372581B1
公开(公告)日：2002-04-16
申请号：US09403356
申请日：1999-10-18
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28238 , H01L29/513 , H01L29/518
摘要： A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.
摘要翻译： 氮化半导体器件的栅极氧化物层的方法包括在硅衬底上的化学生长，其厚度为1nm的天然氧化硅层; 在温度<= 700℃和压力水平<= 104Pa下用气体NO处理涂覆有天然氧化硅层的所述衬底，以获得氮化的天然氧化硅层; 以及栅氧化层的生长。 该方法适用于PMOS器件。鉴于本说明书，本发明的各个方面的进一步修改和替代实施例对于本领域技术人员将是显而易见的。 因此，该描述仅被解释为说明性的，并且是为了教导本领域技术人员进行本发明的一般方式的目的。 应当理解，本文示出和描述的本发明的形式将被视为当前优选的实施例。 元件和材料可以代替本文所示出和描述的那些，部件和工艺可以颠倒，并且本发明的某些特征可以独立地使用，这一切如本领域技术人员在获得本说明书的益处之后显而易见的 本发明。 在不脱离如所附权利要求所述的本发明的精神和范围的情况下，可以对本文所述的元件进行改变。
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