公开(公告)号：US3657614A

公开(公告)日：1972-04-18

申请号：US3657614D

申请日：1970-06-15

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R

IPC: H01L27/088 ,  H01L11/14

CPC classification number: H01L27/088

Abstract: A high density MIS array on a single substrate wherein at least two series coupled transistors are provided comprising two diffused junctions separated laterally in one surface of the substrate with a pair of spaced apart gate electrodes located intermediate thereof and separated therefrom by a first layer of insulated material. Another or top electrode separated from the pair of gate electrodes by a second layer of insulated material extends above and across to at least the closest edge of the two diffused junctions. A bias potential is applied between the substrate and the top electrode whereby field induced regions and respective P-N junctions are generated in the surface of the substrate between the diffused junctions in the region not subtended by the two gate electrodes. Two MIS transistors result having a common field induced junction therebetween, said common field induced junction acting as the drain for one transistor and the source for the other transistor.

Abstract translation: 在单个衬底上的高密度MIS阵列，其中提供至少两个串联耦合晶体管，其包括在衬底的一个表面中横向分离的两个扩散结，其中位于其中间的一对间隔开的栅电极，并通过第一绝缘层隔开 材料。 通过第二绝缘材料层与一对栅电极分离的另一个或顶部电极在两个扩散结的至少最靠近的边缘上方并且穿过至少最接近两个扩散结的边缘。 在衬底和顶部电极之间施加偏置电位，由此在不被两个栅电极对向的区域中的扩散结之间的衬底表面中产生场感应区域和相应的P-N结。 两个MIS晶体管在其之间产生共同的场感应结，所述公共场感应结用作一个晶体管的漏极和另一个晶体管的源极。

公开(公告)号：US3430065A

公开(公告)日：1969-02-25

申请号：US3430065D

申请日：1965-08-09

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R

IPC: H03K19/084 ,  H03K19/34 ,  H03K19/36

CPC classification number: H03K19/084

公开(公告)号：US3641511A

公开(公告)日：1972-02-08

申请号：US3641511D

申请日：1970-02-06

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R ,  LANCASTER EDGAR D JR

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/092 ,  H01L27/112 ,  H03K3/356 ,  G11C11/40 ,  G11C5/02 ,  G11C7/00

CPC classification number: H01L27/092 ,  G11C11/412 ,  G11C11/417 ,  H01L27/112 ,  H03K3/356156

Abstract: A random access nondestructive voltage readout complementary MOSFET memory fabricated on a single integrated circuit ''''chip, '''' including not only a plurality of identical memory cells arranged in a matrix array, but also the digital address decoding logic circuitry as well as the input/output buffer circuitry including data line driver circuits insulating the memory cell array from external data lines and input/output control logic circuits insulating the address decoding logic circuitry and the data line driver circuits from external read/write control and strobe input sources. Both N-channel and P-channel MOSFETS are fabricated adjacent to one another as complementary pairs on the same ''''chip'''' with the exclusion of at least one guard ring diffusion region between adjacent drain diffusion regions of the complementary pairs by the inclusion of a relatively thick oxide layer (15-20 KA.) which operates to minimize internal interconnection line capacitance and parasitic surface channels. The data line drivers are bidirectional to provide nondestructive readout, fast readout response, noisy immunity and low-input capacitance. Each memory cell is comprised of two pairs of complementary MOSFETS coupled together as cross-coupled inverter circuits. Additionally, each cell is provided with a pair of parallely connected complementary MOSFETS acting as an input/output transmission switch and are coupled to a common input/output internal data line and operated by separate address command signals from the address decoding logic circuit. Another pair of parallely connected complementary MOSFETS are coupled to the memory cell as a feedback transmission switch and are operated by still other separate address command signals from the address decoding logic circuit. The address command logic utilized to operate the parallely connected pairs comprising the input/output transmission switch and the feedback transmission switch is timed to permit nondestructive readout of the memory cell.

公开(公告)号：US3584264A

公开(公告)日：1971-06-08

申请号：US3584264D

申请日：1968-03-21

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： MCLOUSKI RAYMOND M ,  CRICCHI JAMES R

IPC: H01L21/316 ,  H01L23/29 ,  H01L23/31 ,  H01L1/14

CPC classification number: H01L23/291 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31625 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/043 ,  Y10S148/118 ,  H01L2924/00

Abstract: An encapsulated microcircuit device including a wafer of semiconductor material, an intermediate coating of silicon dioxide on the wafer, a metal interconnect pattern on the silicon dioxide coating and having portions extending therethrough to the wafer, an outer coating on the intermediate coating and on the metal interconnect pattern and being composed of glass and a metal oxide and having a coefficient of thermal expansion substantially equal to that of the interconnect pattern and the silicon dioxide coating.

公开(公告)号：US3539880A

公开(公告)日：1970-11-10

申请号：US3539880D

申请日：1968-12-31

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： SQUIRE JON S ,  CRICCHI JAMES R

IPC: H01L21/00 ,  H01L23/29 ,  H01L23/485 ,  H01L27/00 ,  H01L19/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/291 ,  H01L27/00 ,  H01L2924/0002 ,  Y10T29/49105 ,  Y10T29/49156 ,  H01L2924/00

公开(公告)号：US3877058A

公开(公告)日：1975-04-08

申请号：US42453073

申请日：1973-12-13

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R

IPC: G11C17/00 ,  G11C13/04 ,  G11C16/04 ,  G11C27/04 ,  H01L21/8247 ,  H01L27/144 ,  H01L27/146 ,  H01L29/788 ,  H01L29/792 ,  H01L31/10 ,  H01L15/00 ,  H01L11/14

CPC classification number: H01L27/14643 ,  G11C13/048 ,  G11C16/0466 ,  H01L27/1443

Abstract: An MNOS radiation charge transfer memory device wherein charge generated in a semiconductor body by radiation is transferred through a surface inversion layer and an oxide layer to a silicon-nitride-oxide interface for storage. The readout voltage is proportional to the charge density stored. Therefore, it is possible to realize a gain proportional to the ratio of the junction sensor area to the nitride-oxide memory gate area. The device may be applied to optically accessed digital or analog memories.

公开(公告)号：US3680062A

公开(公告)日：1972-07-25

申请号：US3680062D

申请日：1970-06-24

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R

IPC: G11C16/04 ,  G11C11/40

CPC classification number: G11C16/0466

Abstract: A non-volatile memory employing variable threshold voltage field effect transistors as main memory storage elements is utilized in a fuse system for detonating explosive projectiles. Each transistor is selectively set to first and second stable threshold voltages by applying positive or negative polarizing voltages between the gate and the source of the transistor. The threshold voltage state of the transistor is determined by applying a read voltage having a magnitude greater than the first stable threshold voltage and less than the second stable threshold voltage. The transistor is activated only if it has assumed the first threshold voltage. A buffer shift register is provided for receiving a serial data input and producing a corresponding parallel output of positive and negative polarizing voltages. The information in the buffer shift register is transferred to the main memory by a plurality of write transmission gates and is transferred from the main memory to the shift register by a plurality of read transmission gates. A fire command generated by the firing of a projectile, such as an artillery shell, transfers the information in the main memory to a counter. The counter is then operated until overflow occurs and a signal is generated by the counter to detonate the explosive projectile.

Abstract translation: 使用可变阈值电压场效应晶体管作为主存储器存储元件的非易失性存储器用于引爆爆炸性射弹的保险丝系统。 通过在晶体管的栅极和源极之间施加正或负极化电压，将每个晶体管选择性地设置为第一和第二稳定阈值电压。 通过施加具有大于第一稳定阈值电压且小于第二稳定阈值电压的幅度的读取电压来确定晶体管的阈值电压状态。 仅当晶体管已经采用第一阈值电压时才激活晶体管。 提供缓冲移位寄存器用于接收串行数据输入并产生正和负极化电压的对应并行输出。 缓冲移位寄存器中的信息通过多个写传输门传送到主存储器，并通过多个读传输门从主存储器传送到移位寄存器。 通过射击炮弹（例如炮弹）产生的火命令将主存储器中的信息传送到计数器。 然后运行计数器，直到发生溢出，并且由计数器产生信号以引爆爆炸性射弹。

公开(公告)号：US3898603A

公开(公告)日：1975-08-05

申请号：US84616569

申请日：1969-07-30

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R ,  LYTLE WALTER J ,  HERMAN DAVID S

IPC: H03K19/177 ,  H01H69/02 ,  H01H85/046 ,  H01L21/00 ,  H01L21/82 ,  H01L23/525 ,  H01H85/04

CPC classification number: H01L23/5256 ,  H01H69/022 ,  H01H85/046 ,  H01L21/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit wafers are provided with links of such nature as to render the wafers electrically programmable without reliance upon joule-heating melting to destroy the links in the desired locations. The joule-heating melting previously used with electrically programmable wafers causes undesired effects such as volatilization, unwanted diffusions, etc. With use of photoengraving and etching techniques, there can be produced upon a wafer, according to this invention, links of novel kind that respond, through a defect-aided electromigration effect, to current densities below those required with the hitherto-known links fusible by joule heating. The novel links are of metal, typically about 0.4 mil wide and 50-1500 Angstroms thick, being used to join permanent connection members on the integrated circuit wafer, with the permanent connection members being on the order of 5000 Angstroms thick.

Abstract translation: 集成电路晶片设置有这样的链接，使得晶片可以电可编程，而不依赖于焦耳加热熔化以破坏期望位置中的链路。 以前与电可编程晶片一起使用的焦耳加热熔化导致不期望的影响，例如挥发，不期望的扩散等。使用光刻和蚀刻技术，可以在根据本发明的晶片上产生响应的新型链接 通过缺陷辅助的电迁移效应，到当前密度低于通过焦耳加热可熔化的迄今为止已知的连接所需的密度。 新颖的链接是金属的，通常为约0.4密耳宽和50-1500埃厚，用于连接集成电路晶片上的永久连接构件，永久连接构件的厚度约为5000埃。

公开(公告)号：US3683335A

公开(公告)日：1972-08-08

申请号：US3683335D

申请日：1970-06-24

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R ,  BEYDLER WILLIAM W

IPC: G11C16/04 ,  G11C11/40 ,  G11C5/06

CPC classification number: G11C16/0466

Abstract: A metal insulated semiconductor (MIS) field effect transistor is operated in a gate-to-source mode. The voltage threshold of conduction of the transistor is variable and is switched between two different stable threshold conditions in response to application of corresponding, different predetermined values of polarizing voltages applied between the gate and source terminals. Determination of the threshold condition to which the transistor is switched is effected by applying a read voltage to the gate of the transistor intermediate the voltage threshold levels and sensing the current flow between the source and drain. Since the sense voltage is less than the polarizing voltage for either condition of switching, the preset threshold condition is maintained. The transistor therefore exhibits a non-volatile memory capability. A plurality of the transistors are employed in a memory array and may be readily fabricated in integrated circuit form.

Abstract translation: 金属绝缘半导体（MIS）场效应晶体管以栅极到源极的方式工作。 晶体管的导通电压阈值是可变的，并且响应于施加在栅极和源极端子之间施加相应的不同预定值的极化电压，在两个不同的稳定阈值条件之间切换。 通过将晶体管的栅极施加到电压阈值电平的中间并感测源极和漏极之间的电流来实现晶体管切换到的阈值条件的确定。 由于感测电压小于切换条件下的极化电压，因此保持预设的阈值条件。 因此，晶体管表现出非易失性存储器能力。 在存储器阵列中采用多个晶体管，并且可以容易地以集成电路形式制造晶体管。

公开(公告)号：US3602705A

公开(公告)日：1971-08-31

申请号：US3602705D

申请日：1970-03-25

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES R ,  CAVAR GUSTAV

IPC: G06F7/50 ,  G06F7/501 ,  G06F7/385 ,  G06F7/48

CPC classification number: G06F7/5016 ,  G06F2207/4816

Abstract: A combinatorial circuit utilizing transmission switch logic wherein the entire arithmetic function including the generation of a sum and output carry signal occurs simultaneously in a twolevel logic configuration of interconnected switches which are preferably metal oxide semiconductor field effect transistors. The two-level logic configuration permits shorter propagation time thereby enabling a high speed of operation. Additionally, the propagation of the output carry signal is increased by controlling the gating of the carry signal independently of the carry input. MOSFETS are preferably utilized because little or no quiescent current flow occurs therein realizing minimum power dissipation.