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51 条记录 (耗时 0.026 秒)

    Threshold/voltage detection circuit
    1.
    发明授权
    Threshold/voltage detection circuit 失效
    阈值/电压检测电路

    公开(公告)号：US5278458A

    公开(公告)日：1994-01-11

    申请号：US807545

    申请日：1991-12-13

    申请人： Wayland B. Holland ,  Gary L. Howe ,  John F. Schreck

    发明人： Wayland B. Holland ,  Gary L. Howe ,  John F. Schreck

    IPC分类号： H03K3/3565 ,  H03K17/30 ,  H05K3/01 ,  H05K5/153

    CPC分类号： H03K17/302 ,  H03K3/3565

    摘要： One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node. Each of the first, second and third switching devices are of like conductivity type, and the second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold.

    摘要翻译： 本发明的一个方面包括用于检测输入电压何时超过预定阈值的电路。 用于检测的电路包括用于接收输入电压的输入端。 此外，电路包括多个开关装置，其中每个开关装置包括用于限定可变导电路径的第一和第二端子，以及用于接收控制所述可变导电路径的信号的第三端子。 多个开关装置包括三个开关装置。 第一开关装置具有耦合到输入的第一端子和耦合到第一节点的第二端子。 第二交换设备具有耦合到第一节点的第一终端和耦合到第二节点的第二终端。 最后，第三交换设备具有耦合到第二节点的第一终端。 第一，第二和第三开关装置中的每一个具有类似导电类型，如果输入电压低于预定阈值，则第二节点提供第一电压，并且如果输入电压高于预定阈值则提供第二电压。

    Segmented, multiple-decoder memory array and method for programming a memory array
    5.
    发明授权
    Segmented, multiple-decoder memory array and method for programming a memory array 失效
    分段的多解码器存储器阵列和用于编程存储器阵列的方法

    公开(公告)号：US5313432A

    公开(公告)日：1994-05-17

    申请号：US790122

    申请日：1991-11-12

    申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

    发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

    IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

    CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

    摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

    摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

    Nonvolatile memory array wordline driver circuit with voltage translator circuit
    6.
    发明授权
    Nonvolatile memory array wordline driver circuit with voltage translator circuit 失效
    具有电压转换电路的非易失性存储器阵列字线驱动电路

    公开(公告)号：US5287536A

    公开(公告)日：1994-02-15

    申请号：US9276

    申请日：1993-01-22

    申请人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

    发明人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

    IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/06 ,  G11C5/14

    CPC分类号： G11C16/08 ,  G11C16/12

    摘要： A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed.

    摘要翻译： 用于驱动浮栅型EEPROM单元阵列中的字线或字线组的电路包括用于切换正读取电压的读取驱动器子电路，用于切换正编程电压的程序驱动器子电路和可选地用于切换负极的子电路 擦除电压。 当连接到高电容字线时，读驱动器子电路可以使用相对较短的沟道晶体管来构造，用于相对高速的操作。 另一方面，程序驱动器子电路可以使用相对长的沟道晶体管构成，并且那些长沟道晶体管可以远离存储器单元和读取驱动器电路位于存储器芯片上。 P沟道隔离晶体管用于在运行期间隔离未使用的电路。 程序驱动器子电路中的电压转换器具有减小超过这些晶体管的击穿电压的可能性的晶体管配置。 还公开了非易失性存储单元阵列的编程方法。

    Method and apparatus for determining the field position of an integrated circuit within a reticle area
    8.
    发明授权
    Method and apparatus for determining the field position of an integrated circuit within a reticle area 失效
    用于确定标线片区域内的集成电路的场位置的方法和装置

    公开(公告)号：US5151880A

    公开(公告)日：1992-09-29

    申请号：US450808

    申请日：1989-12-14

    申请人： John F. Schreck ,  Phat C. Truong

    发明人： John F. Schreck ,  Phat C. Truong

    IPC分类号： G11C16/20

    CPC分类号： G11C16/20

    摘要： Apparatus for determining the field position (00, 01, 10, 11) of an integrated circuit (18) within a reticle area (12) which contains a plurality of such integrated circuits (14-20) includes a plurality of memory cells (76, 80) formed within the integrated circuit (18) for encoding the field position. Circuitry (40, 94, 100, 104, 106) is provided for reading the states of the memory cells to ascertain the field position.

    摘要翻译： 用于确定包含多个这种集成电路（14-20）的标线片区域（12）内的集成电路（18）的场位置（00,01,10,11）的装置包括多个存储单元（76 ，80）形成在集成电路（18）内，用于对场位置进行编码。 电路（40,94,100,104,106）被提供用于读取存储器单元的状态以确定场位置。

    Offset floating gate EPROM memory cell
    9.
    发明授权
    Offset floating gate EPROM memory cell 失效
    偏移浮栅EPROM存储单元

    公开(公告)号：US4750024A

    公开(公告)日：1988-06-07

    申请号：US830160

    申请日：1986-02-18

    申请人： John F. Schreck

    发明人： John F. Schreck

    IPC分类号： H01L21/8247 ,  H01L21/762 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/40 ,  H01L27/02 ,  H01L29/04

    CPC分类号： H01L27/115 ,  H01L21/76216 ,  H01L29/7885

    摘要： An electrically programmable read only memory device formed in a face of a semiconductor substrate of a first conductivity type which includes a pair of spaced apart thick oxide isolation regions defining an elongated channel of the substrate therebetween. A floating gate of conductive material overlies a portion of one of the isolation regions and a first portion of the elongated channel being separated from the oxide isolation and channel regions by an insulator layer. A control layer of conductive material extends over the channel and the floating gate separated from both of the latter by an insulator layer. Buried diffused regions are located below each oxide isolation region.

    摘要翻译： 一种电可编程只读存储器件，形成在第一导电类型的半导体衬底的表面上，该第一导电类型的半导体衬底包括一对间隔开的厚度的氧化物隔离区域，该氧化物隔离区域限定了衬底之间的细长通道。 导电材料的浮栅覆盖在隔离区之一的一部分上，并且细长通道的第一部分通过绝缘体层与氧化物隔离和沟道区分离。 导电材料的控制层在沟道上延伸，浮动栅极通过绝缘体层与后者分离。 掩埋扩散区位于每个氧化物隔离区的下方。