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    Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
    1.
    发明授权
    Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer 失效
    制造具有氧化多孔硅隔离层的半导体结构的方法

    公开(公告)号：US4532700A

    公开(公告)日：1985-08-06

    申请号：US604563

    申请日：1984-04-27

    申请人： Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

    发明人： Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

    IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L21/20

    CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

    摘要： A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide having a predetermined thickness.

    摘要翻译： 提供了一种用于制造在硅体一侧具有介电隔离的硅区的半导体结构的方法。 这通过在硅体中形成一组掩埋区域和具有使其阳极蚀刻比硅体的剩余部分更慢的特性的一组表面区域来实现。 这两组区域限定了硅体中的阳极蚀刻部分以形成多孔硅区域，这些硅区域被氧化以形成将硅表面区域与硅体的其余部分隔离的隔离结构。 通常在P型硅体中，掩埋和表面区域是通过离子注入形成的N型区域。 使用这些N型区域来控制P型材料暴露于阳极蚀刻溶液和形成多孔硅区域，获得的结构是其中表面单晶硅区域与硅体的其余部分通过 均匀的具有预定厚度的二氧化硅层。

    Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
    2.
    发明授权
    Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step 失效
    使用单个掩蔽步骤制造具有对准场掺杂的双阱CMOS半导体结构的工艺

    公开(公告)号：US4558508A

    公开(公告)日：1985-12-17

    申请号：US660673

    申请日：1984-10-15

    申请人： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

    发明人： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

    IPC分类号： H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/78

    CPC分类号： H01L21/76218 ,  H01L21/033 ,  H01L21/823892 ,  H01L29/0638 ,  H01L27/0928 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/10 ,  Y10S148/157

    摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

    摘要翻译： 制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。 光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体） 在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。 结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。 然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。

    Method of producing a thin silicon-on-insulator layer
    3.
    发明授权
    Method of producing a thin silicon-on-insulator layer 失效
    制造薄的绝缘体上硅层的方法

    公开(公告)号：US4601779A

    公开(公告)日：1986-07-22

    申请号：US747746

    申请日：1985-06-24

    申请人： John R. Abernathey ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Thomas O. Sedgwick ,  Scott; R. Stiffler

    发明人： John R. Abernathey ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Thomas O. Sedgwick ,  Scott; R. Stiffler

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L21/316 ,  H01L21/2007

    摘要： A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

    摘要翻译： 形成半导体器件的薄硅层的形成方法。 在硅衬底上生长外延层，并且将氧或氮离子注入到外延层中以在其中形成掩埋的蚀刻停止层。 在外延层上生长氧化物层，并且用于与机械支撑晶片形成结合。 使用研磨和/或HNA去除硅衬底，使用EDP，EPP或KOH除去外延的上部，并使用非选择性蚀刻去除蚀刻停止。 外延的剩余部分形成薄硅层。 由于注入离子的均匀性，薄硅层具有非常均匀的厚度。

    Method of chemically mechanically polishing an electronic component
    5.
    发明授权
    Method of chemically mechanically polishing an electronic component 失效
    化学机械抛光电子元件的方法

    公开(公告)号：US5573633A

    公开(公告)日：1996-11-12

    申请号：US557225

    申请日：1995-11-14

    申请人： Jeffrey P. Gambino ,  Mark A. Jaso ,  Larry A. Nesbit

    发明人： Jeffrey P. Gambino ,  Mark A. Jaso ,  Larry A. Nesbit

    IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

    摘要： A method of forming interlevel studs of at least two different materials in an insulating layer on a semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias are formed through the BPSG layer in array areas. A thin doped poly layer is deposited on the surface of the BPSG layer. The structure is annealed and vias are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.

    摘要翻译： 在半导体晶片上的绝缘层中形成至少两种不同材料的层间柱的方法。 在线前端（FEOL）结构上形成BPSG绝缘层后，BPSG层被化学磨光。 通过阵列区域中的BPSG层形成通孔。 在BPSG层的表面上沉积薄的掺杂多晶硅层。 结构退火，并在支撑区域形成通孔。 通过通孔将掺杂剂植入支撑区域。 在退火到漫射注入掺杂剂之后，在多层上形成金属层。 然后，该结构被化学研磨回到多层。 最终的化学抛光步骤除去多层，将金属螺柱留在支撑区域和阵列区域中的多芯金属芯柱螺柱。

    Double-gate FETs (Field Effect Transistors)
    6.
    发明授权
    Double-gate FETs (Field Effect Transistors) 失效
    双栅极FET（场效应晶体管）

    公开(公告)号：US07250347B2

    公开(公告)日：2007-07-31

    申请号：US10905979

    申请日：2005-01-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

    摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

    摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

    Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
    7.
    发明授权
    Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask 失效
    使用线位线接触掩模形成垂直DRAM阵列的位线触点的结构和方法

    公开(公告)号：US06767781B2

    公开(公告)日：2004-07-27

    申请号：US10667308

    申请日：2003-09-23

    申请人： Larry A. Nesbit ,  Jonathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

    发明人： Larry A. Nesbit ,  Jonathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

    IPC分类号： H01L218238

    CPC分类号： H01L27/10885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888

    摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

    摘要翻译： 使用位线接触掩模形成垂直DRAM阵列的位线接触的位线接触和方法。 在该方法中，形成栅极导体线。 在栅极导体线上沉积氧化物层，并且在氧化物层的部分上形成位线接触掩模。 蚀刻位线接触掩模，并且在衬底上沉积硅层。 位于硅层上的位线层被沉积。 对位线层进行掩模和蚀刻操作。 在硅层和位线（M0）层的非蚀刻部分的侧面上沉积M0金属以形成左和右位线。

    Method of forming self-limiting polysilicon LOCOS for DRAM cell
    8.
    发明授权
    Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
    DRAM单元形成自限多晶硅LOCOS的方法

    公开(公告)号：US06309924B1

    公开(公告)日：2001-10-30

    申请号：US09585898

    申请日：2000-06-02

    申请人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    发明人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861 ,  H01L27/10867

    摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

    摘要翻译： 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。 然后将一层非晶硅沉积在氮化物衬垫上。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。