公开(公告)号：US20110217814A1

公开(公告)日：2011-09-08

申请号：US13125502

申请日：2008-10-23

申请人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

发明人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

IPC分类号： H01L21/78

CPC分类号： H01L21/67092 ,  H01L21/568 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68322 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

摘要翻译： 提供了形成电子组件的方法。 提供具有嵌入其中的多个电子部件的器件基板。 使用粘合剂材料将装置基板附接到载体基板。 通过器件基板形成多个切口，以将器件基板分成多个部分。 多个部分中的每一个包括至少一个电子部件。 在远离载体基板的方向上对多个部分中的每一个施加力以从载体基板移除多个部分。

公开(公告)号：US09142434B2

公开(公告)日：2015-09-22

申请号：US13125502

申请日：2008-10-23

申请人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

发明人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/67092 ,  H01L21/568 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68322 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

摘要翻译： 提供了形成电子组件的方法。 提供具有嵌入其中的多个电子部件的器件基板。 使用粘合剂材料将装置基板附接到载体基板。 通过器件基板形成多个切口，以将器件基板分成多个部分。 多个部分中的每一个包括至少一个电子部件。 在远离载体基板的方向上对多个部分中的每一个施加力以从载体基板移除多个部分。

公开(公告)号：US08216918B2

公开(公告)日：2012-07-10

申请号：US12842562

申请日：2010-07-23

申请人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

发明人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

IPC分类号： H01L21/00 ,  H01L21/322

CPC分类号： H01L21/6835 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2203/1469

摘要： A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

摘要翻译： 使用一种方法来形成封装的半导体器件。 具有活性表面的半导体器件被放置在电路板的开口中。 电路板具有第一主表面和具有开口的第二主表面，在第一主表面和第二主表面之间延伸的第一通孔，第一接触垫在第一主表面处终止通孔，第二接触垫终止 第二个主要表面的通孔。 电介质层被施加在半导体器件和电路板的第二主表面上。 在电介质层上形成互连层。 互连层具有电连接到第二接触焊盘的第二通孔，电连接到半导体器件的有源表面的第三通孔，暴露表面和暴露表面处的第三接触焊盘。

公开(公告)号：US20120021565A1

公开(公告)日：2012-01-26

申请号：US12842562

申请日：2010-07-23

申请人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

发明人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

IPC分类号： H01L21/58

CPC分类号： H01L21/6835 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2203/1469

摘要： A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

摘要翻译： 使用一种方法来形成封装的半导体器件。 具有活性表面的半导体器件被放置在电路板的开口中。 电路板具有第一主表面和具有开口的第二主表面，在第一主表面和第二主表面之间延伸的第一通孔，第一接触垫在第一主表面处终止通孔，第二接触垫终止 第二个主要表面的通孔。 电介质层被施加在半导体器件和电路板的第二主表面上。 在电介质层上形成互连层。 互连层具有电连接到第二接触焊盘的第二通孔，电连接到半导体器件的有源表面的第三通孔，暴露表面和暴露表面处的第三接触焊盘。

公开(公告)号：US09034697B2

公开(公告)日：2015-05-19

申请号：US13182710

申请日：2011-07-14

申请人： Zhiwei Gong ,  Jianwen Xu ,  Wei Gao ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Jianwen Xu ,  Wei Gao ,  Scott M. Hayes

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/568 ,  H01L21/4821 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

摘要翻译： 公开了一种用于制造半导体封装的方法，其包括提供引线元件的供应，将多个引线元件安装在引线框架上，直到将预定数量的引线元件放置在引线框架上，以及连接引线上的其它元件 框架到铅元素。

公开(公告)号：US08916421B2

公开(公告)日：2014-12-23

申请号：US13222148

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L21/70 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 一个或多个信号管道耦合到引线框架，引线框架随后嵌入在封装的半导体器件封装中。 信号管道的自由端被暴露，而另一端保持联接到引线框架。 然后，信号导管用作通过封装通孔，在封装的底部和顶部与引线之间的互连或接触之间提供信号承载通路。

公开(公告)号：US08617935B2

公开(公告)日：2013-12-31

申请号：US13220891

申请日：2011-08-30

申请人： Jianwen Xu ,  Zhiwei Gong ,  Scott M. Hayes

发明人： Jianwen Xu ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

摘要翻译： 提供了用于半导体封装背面互连处理的精确对准的机构。 由于半导体管芯被放置在用于密封面板的适当位置，所以在面板中也放置了两个或更多个具有形成在这些管芯的背面或非活性侧上的基准标记的对准管芯。 一旦所有模具和其他部件已经放置在面板上，面板将使用密封剂进行封装。 过多的密封剂（如果有的话）通过诸如背磨的过程被去除。 后研磨工艺将对准模具的背面和这些对准模具上的基准特征曝光。 然后可以将对准裸片上的基准特征用于对准面板上的背面处理操作。

公开(公告)号：US20130052777A1

公开(公告)日：2013-02-28

申请号：US13220891

申请日：2011-08-30

申请人： Jianwen Xu ,  Zhiwei Gong ,  Scott M. Hayes

发明人： Jianwen Xu ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

摘要翻译： 提供了用于半导体封装背面互连处理的精确对准的机构。 由于半导体管芯被放置在用于密封面板的适当位置，所以在面板中也放置了两个或多个具有形成在这些管芯的背面或非活性侧上的基准标记的对准管芯。 一旦所有模具和其他部件已经放置在面板上，面板将使用密封剂进行封装。 过多的密封剂（如果有的话）通过诸如背磨的过程被去除。 后研磨工艺将对准模具的背面和这些对准模具上的基准特征曝光。 然后可以将对准裸片上的基准特征用于对准面板上的背面处理操作。

公开(公告)号：US20130049182A1

公开(公告)日：2013-02-28

申请号：US13222148

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L21/70 ,  H01L21/50

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 一个或多个信号管道耦合到引线框架，引线框架随后嵌入在封装的半导体器件封装中。 信号管道的自由端被暴露，而另一端保持联接到引线框架。 然后，信号导管用作通过封装通孔，在封装的底部和顶部与引线之间的互连或接触之间提供信号承载通路。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。