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    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
    1.
    发明申请
    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays 审中-公开
    具有纳米功能的存储器件和各向异性电荷携带阵列

    公开(公告)号：US20080026532A1

    公开(公告)日：2008-01-31

    申请号：US11850127

    申请日：2007-09-05

    申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7887 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    Nano-enabled memory devices and anisotropic charge carrying arrays
    2.
    发明申请
    Nano-enabled memory devices and anisotropic charge carrying arrays 审中-公开
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US20070247904A1

    公开(公告)日：2007-10-25

    申请号：US11766980

    申请日：2007-06-22

    申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    IPC分类号： G11C16/04

    CPC分类号： H01L29/7887 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    Nano-enabled memory devices and anisotropic charge carrying arrays
    3.
    发明申请
    Nano-enabled memory devices and anisotropic charge carrying arrays 审中-公开
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US20050202615A1

    公开(公告)日：2005-09-15

    申请号：US10796413

    申请日：2004-03-10

    申请人： Xiangfeng Duan ,  Chunming Niu ,  David Stumbo ,  Calvin Chow

    发明人： Xiangfeng Duan ,  Chunming Niu ,  David Stumbo ,  Calvin Chow

    IPC分类号： H01L21/8234

    CPC分类号： G11C16/0408 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A thin film of nanoelements is formed on the substrate above a channel region. A gate contact is formed on the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device, nanoelements are present having a plurality of charge injection voltages, to provide multiple states. In another aspect, a printing device includes a charge diffusion layer that includes a matrix containing a plurality of nanoelements configured to be anisotropically electrically conductive through the charge diffusion layer to transfer charge to areas of the first surface with reduced lateral charge spread.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 在通道区域上方的衬底上形成纳米元素的薄膜。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在多状态存储器件中，纳米元件具有多个电荷注入电压，以提供多种状态。 另一方面，印刷装置包括电荷扩散层，该电荷扩散层包括通过电荷扩散层构成为各向异性导电的多个纳米元素的基体，以将电荷转移到具有减小的横向电荷扩展的第一表面的区域。

    Nano-enabled memory devices and anisotropic charge carrying arrays
    4.
    发明申请
    Nano-enabled memory devices and anisotropic charge carrying arrays 有权
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US20050201149A1

    公开(公告)日：2005-09-15

    申请号：US11018572

    申请日：2004-12-21

    申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/936 ,  Y10S977/943

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
    5.
    发明申请
    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays 有权
    具有纳米功能的存储器件和各向异性电荷携带阵列

    公开(公告)号：US20070187768A1

    公开(公告)日：2007-08-16

    申请号：US11695728

    申请日：2007-04-03

    申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。