公开(公告)号：US06391666B1

公开(公告)日：2002-05-21

申请号：US09475007

申请日：1999-12-30

申请人： Ya-Hui Huang ,  Chih-Chin Liao ,  Tzong-Dar Her

发明人： Ya-Hui Huang ,  Chih-Chin Liao ,  Tzong-Dar Her

IPC分类号： H01L2166

摘要： The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.

公开(公告)号：US06392425B1

公开(公告)日：2002-05-21

申请号：US09475005

申请日：1999-12-30

申请人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

发明人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

IPC分类号： G01R3102

CPC分类号： G01R1/0483 ,  H01L2224/48463 ,  H01L2224/85181

摘要： A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connections connected one another among the chip pads.

摘要翻译： 具有不粘试验结构的多芯片封装基板由在多芯片封装基板的芯片封装区域外部的外围区域形成的多个不粘附试验点构成。 这些不粘贴的测试点中的每一个都通过多个导电迹线电连接到芯片封装区域中的多个芯片焊盘中的相邻的一个，同时在芯片焊盘之间没有彼此连接的电连接。

公开(公告)号：US06583499B2

公开(公告)日：2003-06-24

申请号：US09861757

申请日：2001-05-21

申请人： Chien-Ping Huang ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  Tzong-Dar Her

IPC分类号： H01L23495

CPC分类号： H01L23/3114 ,  H01L23/49503 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0373 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads has respectively a second upper surface and a corresponding second lower surface coplanar to the surface of the island-like blocks; a chip having an active surface and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surface, the first upper surface and the interlacing slots while exposing the surface of the island-like blocks and the second lower surface of the leads.

摘要翻译： 四边形无铅包装包括：形成具有第一上表面和其上的对应的第一下表面的管芯焊盘，其上形成有多个交缠槽，每个交缠槽延伸到管芯焊盘的边缘以形成多个 岛状块 多个引线设置在管芯焊盘的周边，其中每个引线分别具有与岛状块的表面共面的第二上表面和相应的第二下表面; 芯片，其具有粘附到芯片焊盘的第一上表面上的活性表面和对应的背面; 以及在使岛状块的表面和引线的第二下表面暴露的同时封装芯片，第二上表面，第一上表面和交织槽的模塑料。

公开(公告)号：US06541854B2

公开(公告)日：2003-04-01

申请号：US09894884

申请日：2001-06-29

申请人： Chien-Ping Huang ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  Tzong-Dar Her

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18165 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00 ,  H01L2224/45099

摘要： A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.

公开(公告)号：US06731015B2

公开(公告)日：2004-05-04

申请号：US10026452

申请日：2001-12-27

申请人： Chi-Chuan Wu ,  Tzong-Dar Her

发明人： Chi-Chuan Wu ,  Tzong-Dar Her

IPC分类号： H01L23495

CPC分类号： H01L23/3128 ,  H01L23/36 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A super low profile package with stacked dies comprises a substrate, a heat spreader, a first die, a second die, a molding compound, and a number of solder balls. The substrate has a cavity, a top surface and a bottom surface opposite to the top surface. The heat spreader is connected to the bottom surface of the substrate, and a portion of the heat spreader opposite to the cavity serves as a die pad. The first die seated in the cavity is attached to the die pad while the second die seated in the cavity is attached to the first die, and both dies are wire-bonded to the substrate for electrical connection. The molding compound fills the cavity and encapsulates the first die, the second die, the heat spreader, and part of the bottom surface of the substrate. Numerous solder balls are attached to the bottom surface of the substrate. The benefits resulting from the package of the invention include a reduction of profile, a simple manufacturing process, and a low prime cost.

摘要翻译： 具有堆叠模具的超薄型封装包括基板，散热器，第一模具，第二模具，模塑料和多个焊球。 衬底具有与顶表面相对的空腔，顶表面和底表面。 散热器连接到基板的底表面，散热器与空腔相对的一部分用作管芯焊盘。 安置在空腔中的第一个模具附接到模具垫，而位于空腔中的第二模具附接到第一模具，并且两个模具被引线接合到基板用于电连接。 模制化合物填充空腔并封装第一模具，第二模具，散热器和衬底的底部表面的一部分。 许多焊球附着到基底的底表面上。 由本发明的包装带来的好处包括轮廓的减少，简单的制造过程和低的原始成本。

公开(公告)号：US06650009B2

公开(公告)日：2003-11-18

申请号：US10206720

申请日：2002-07-26

申请人： Tzong-Dar Her ,  Randy H. Y. Lo ,  Chien-Ping Huang

发明人： Tzong-Dar Her ,  Randy H. Y. Lo ,  Chien-Ping Huang

IPC分类号： H01L2302

CPC分类号： H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A structure of a multi chip module package having stacked chips, having at least a substrate, a main chip, a plurality of chip sets, a plurality of spacers, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. A plurality of chips are stacked in the form of laminate on the front surface of the substrate to form a plurality of chip sets, which are located next to the main chip. A plurality of spacers are arranged between each two adjacent chips. The connection between the spacers, the main chip, the chips, and the substrate are achieved by a plurality of glue layers. A plurality of wires are used to electrically connect the chips and the main chip to the substrate. Finally, the front surface of the substrate, the main chip, the spacers, the chips, and the glue layers are encapsulated with a mold compound to accomplish the package.

公开(公告)号：US06525942B2

公开(公告)日：2003-02-25

申请号：US09860421

申请日：2001-05-18

申请人： Chien-Ping Huang ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  Tzong-Dar Her

IPC分类号： H05K720

CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A heat dissipation ball grid array package includes the following elements. A plurality of first thermal ball pads is formed on the underside of a substrate in the area covered by chip. A plurality of second thermal ball pads or a heat dissipation ring is formed outside the first thermal ball pads. A plurality of signal ball pads is formed outside the second thermal ball pads or the heat dissipation ring. The second thermal ball pads or heat dissipation ring is connected to the first thermal ball pads by conductive trace lines. A plurality of first thermal balls is attached to the respective first thermal ball pads. The signal balls are attached to the respective signal ball pads. The first thermal balls and the signal balls are in contact with corresponding contact points on a printed circuit board. A plurality of second thermal balls is attached to the respective second thermal ball pads or the surface of the heat dissipation ring.

公开(公告)号：US06713321B2

公开(公告)日：2004-03-30

申请号：US10305965

申请日：2002-11-29

申请人： Chien-Ping Huang ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  Tzong-Dar Her

IPC分类号： H01L2148

CPC分类号： H01L21/568 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18165 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00 ,  H01L2224/45099

摘要： A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.

摘要翻译： 具有高效率散热效果的超薄型封装包括基板，散热片，模具，电线和塑料模具。 散热片通过散热器的延伸部分粘附到接地环上，并且模具的第一表面附着在散热片上。 另外，模具通过导线连接到基板，塑料模具封装模具，散热器和电线。 本发明的芯片封装尺寸小，散热效率高; 此外，它还降低了生产成本，以消除常规的胶带和脱胶方法。

公开(公告)号：US06593662B1

公开(公告)日：2003-07-15

申请号：US09631343

申请日：2000-08-02

申请人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

发明人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

IPC分类号： H01L2348

CPC分类号： H01L24/33 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.

摘要翻译： 堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。 载体具有与上表面相对的上表面和后表面。 基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。 间隔件位于两个相邻的模具之间。 位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。 导体线分别电连接在管芯和载体的每个接合焊盘之间。 并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。 具有焊球或具有引脚的引线框架的基板适合用作载体。

公开(公告)号：US06291260B1

公开(公告)日：2001-09-18

申请号：US09482758

申请日：2000-01-13

申请人： Chien-Ping Huang ,  April Chen ,  Tzong-Dar Her

发明人： Chien-Ping Huang ,  April Chen ,  Tzong-Dar Her

IPC分类号： H01L2144

CPC分类号： H01L21/481 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A crack-preventive substrate for fabricating a solder mask in a device site region includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. As a result, the crack lines generated on the solder mask layer at the perimeter of the substrate will not develop toward the solder mask in the device site region.

摘要翻译： 用于在器件位置区域制造焊料掩模的防裂衬底包括具有顶表面和底表面的衬底和焊料掩模层。 将基板分为装置位置区域和外围区域。 设置在基板的顶表面和底表面上的焊料掩模层通过在基板的顶表面和底表面上暴露基板的一部分而在基板的顶表面和底表面上形成裸露区域。 并且裸露区域将焊接掩模层分成“器件区域焊料掩模层”和“外围区域焊接掩模层”。 结果，在衬底的周边处的焊料掩模层上产生的裂纹线将不会朝向器件位置区域中的焊接掩模发展。