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    Multiple layer semiconductor circuit module
    1.
    发明授权
    Multiple layer semiconductor circuit module 失效
    多层半导体电路模块

    公开(公告)号：US5160907A

    公开(公告)日：1992-11-03

    申请号：US753049

    申请日：1991-08-30

    申请人： Yasuharu Nakajima ,  Akira Inoue

    发明人： Yasuharu Nakajima ,  Akira Inoue

    IPC分类号： H01L21/3205 ,  H01L21/60 ,  H01L21/66 ,  H01L23/498 ,  H01L23/52 ,  H01L23/66 ,  H01L27/00

    CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L24/01 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011

    摘要： A multiple layer semiconductor circuit module includes a semiconductor substrate including opposed first and second surfaces and side walls; a first circuit disposed on the first surface of the substrate including a plurality of conductors, at least one of the conductors extending on the first surface of the substrate to one of the side walls; a first electrically insulating layer disposed on the first surface of the substrate, covering the first circuit, and including a second surface adjacent to the first surface of the substrate, an opposed first surface, and side walls; a second circuit disposed on the first surface of the first layer including a plurality of conductors, at least one of the conductors extending on the first surface of the first layer to one of the side walls; a second electrically insulating layer disposed on the first surface of the first layer, covering the second circuit, and including a second surface adjacent to the first surface of the first layer, an opposed first surface, and side walls; a third circuit disposed on the first surface of the second layer including a plurality of conductors, at least one of the conductors extending on the first surface of the second layer to one of the side walls; and at least one electrical conductor disposed on at least one of the side walls of the substrate and the first and second insulating layers electrically interconnecting the first, second, and third circuits.

    摘要翻译： 多层半导体电路模块包括：包括相对的第一和第二表面和侧壁的半导体衬底; 设置在所述基板的包括多个导体的所述第一表面上的第一电路，所述导体中的至少一个在所述基板的所述第一表面上延伸到所述侧壁之一; 第一电绝缘层，设置在所述基板的第一表面上，覆盖所述第一电路，并且包括邻近所述基板的第一表面的第二表面，相对的第一表面和侧壁; 设置在第一层的第一表面上的第二电路包括多个导体，至少一个导体在第一层的第一表面上延伸到一个侧壁; 第二电绝缘层，设置在第一层的第一表面上，覆盖第二电路，并且包括与第一层的第一表面相邻的第二表面，相对的第一表面和侧壁; 设置在第二层的第一表面上的第三电路包括多个导体，至少一个导体在第二层的第一表面上延伸到侧壁中的一个; 以及设置在所述基板的至少一个侧壁上的至少一个电导体，并且所述第一和第二绝缘层将所述第一，第二和第三电路电连接。

    Method for testing semiconductor element
    3.
    发明授权
    Method for testing semiconductor element 失效
    半导体元件测试方法

    公开(公告)号：US5905384A

    公开(公告)日：1999-05-18

    申请号：US779363

    申请日：1997-01-06

    申请人： Akira Inoue ,  Yasuharu Nakajima ,  Yukio Ohta ,  Hiroto Matsubayashi

    发明人： Akira Inoue ,  Yasuharu Nakajima ,  Yukio Ohta ,  Hiroto Matsubayashi

    IPC分类号： G01R31/26 ,  H01L21/66

    CPC分类号： G01R31/2625

    摘要： An apparatus of testing a semiconductor element applies pulsed voltages synchronized with each other, respectively, to a gate and a drain of a semiconductor element being tested and measures current flowing through the semiconductor element in response to the pulsed voltages thus applied. The testing apparatus produces pulsed I-V characteristics considering the influences of self heating and surface energy levels of the semiconductor element and RF swing along a load line during large signal operation.

    摘要翻译： 测试半导体元件的装置将被测量的半导体元件的栅极和漏极分别施加相互同步的脉冲电压，并响应于所施加的脉冲电压来测量流过半导体元件的电流。 考虑到在大信号操作期间，自加热和半导体元件的表面能级以及负载线上的RF摆动的影响，测试装置产生脉冲I-V特性。

    Tab tape and semiconductor chip mounted on tab tape
    4.
    发明授权
    Tab tape and semiconductor chip mounted on tab tape 失效
    贴带和半导体芯片安装在拉链带上

    公开(公告)号：US5767569A

    公开(公告)日：1998-06-16

    申请号：US584293

    申请日：1996-01-11

    申请人： Yukio Ohta ,  Kei Goto ,  Yoshihiro Notani ,  Yasuharu Nakajima ,  Akira Inoue ,  Hiroto Matubayashi

    发明人： Yukio Ohta ,  Kei Goto ,  Yoshihiro Notani ,  Yasuharu Nakajima ,  Akira Inoue ,  Hiroto Matubayashi

    IPC分类号： H01L21/60 ,  H01L21/603 ,  H01L23/485 ,  H01L23/495 ,  H01L23/50 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/49572 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/50 ,  H01L24/83 ,  H01L2224/11552 ,  H01L2224/13099 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/19042 ,  H01L2924/19043

    摘要： The method for mounting a semiconductor chip comprises disposing conductive thermoplastic polyimide as a bonding material between an inner lead of the TAB tape and an external connecting electrode of the semiconductor chip, applying pressure to the conductive thermoplastic polyimide by a wedge with heating by a hot stage via the semiconductor chip. The semiconductor chip comprises the external connecting electrode adhered the conductive thermoplastic polyimide. The method for fabricating the semiconductor chip comprises forming a signal line and a protective film, forming an electrode pad on the signal line not provided the protective film, forming a conductive thermoplastic polyimide layer on the semiconductor wafer by spin coating, forming a resist on the conductive thermoplastic polyimide layer and performing an etching with using the resist as a mask. The inner lead of the TAB tape is made of conductive thermoplastic polyimide, not gilded. The flip-chip mounting substrate comprises a semiconductor chip connecting electrode comprising a signal line made of conductive thermoplastic polyimide, a protective film protecting the signal line, and adhering conductive thermoplastic polyimide on the signal line not providing the protective film. The microwave device comprises mounting the semiconductor chip in the inner lead of the TAB tape by adhering the external connecting electrode of the semiconductor chip to the inner lead of the TAB tape. Therefore, it is not required using high cost material for mounting the semiconductor chip, so that reducing in cost is accomplished.

    摘要翻译： 用于安装半导体芯片的方法包括将导电热塑性聚酰亚胺作为接合材料布置在TAB带的内引线和半导体芯片的外部连接电极之间，通过加热阶段通过楔形件向导电热塑性聚酰亚胺施加压力 通过半导体芯片。 半导体芯片包括附着有导电性热塑性聚酰亚胺的外部连接电极。 制造半导体芯片的方法包括形成信号线和保护膜，在未设置保护膜的信号线上形成电极焊盘，通过旋涂在半导体晶片上形成导电性热塑性聚酰亚胺层，在其上形成抗蚀剂 导电热塑性聚酰亚胺层，并使用抗蚀剂作为掩模进行蚀刻。 TAB带的内引线由导电热塑性聚酰亚胺制成，不镀金。 倒装芯片安装基板包括半导体芯片连接电极，其包括由导电热塑性聚酰亚胺制成的信号线，保护信号线的保护膜，以及在不提供保护膜的信号线上粘附导电热塑性聚酰亚胺。 微波装置包括通过将半导体芯片的外部连接电极粘附到TAB带的内引线上来将半导体芯片安装在TAB带的内引线中。 因此，不需要使用高成本材料来安装半导体芯片，从而实现成本的降低。

    Integrated circuit device
    5.
    发明授权
    Integrated circuit device 失效
    集成电路器件

    公开(公告)号：US5675184A

    公开(公告)日：1997-10-07

    申请号：US587527

    申请日：1996-01-17

    申请人： Hiroto Matsubayashi ,  Kei Goto ,  Yoshihiro Notani ,  Yukio Ohta ,  Akira Inoue ,  Yasuharu Nakajima

    发明人： Hiroto Matsubayashi ,  Kei Goto ,  Yoshihiro Notani ,  Yukio Ohta ,  Akira Inoue ,  Yasuharu Nakajima

    IPC分类号： H01L21/822 ,  H01L21/338 ,  H01L23/66 ,  H01L27/04 ,  H01L27/06 ,  H01L29/812 ,  H01P1/00 ,  H03F1/08 ,  H03F3/60 ,  H01L23/34

    CPC分类号： H01L27/0605 ,  H01L23/66 ,  H03F1/083 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/19105

    摘要： An integrated circuit device includes a substrate; circuit elements including an active element and a bias line for applying a DC bias voltage to the active element, disposed on the substrate; a thermoplastic material layer disposed on a region of the substrate; and a magnetic substance layer disposed on a region of the substrate including a region of the bias line, and adhered to and supported by the thermoplastic material layer. In this structure, the magnetic substance layer can be formed in an appropriate shape and at an appropriate position on the bias line according to the oscillation characteristics of the active element, such as a transistor, and the magnetic substance layer absorbs the frequency components of the oscillation of the active element, whereby oscillation of the active element is easily prevented. Further, since the magnetic substance layer is disposed on the bias line, unwanted increase in the chip area of the integrated circuit device due to the use of the prior art oscillation preventing circuit is avoided.

    摘要翻译： 集成电路器件包括衬底; 电路元件，包括有源元件和偏置线，用于向置于基板上的有源元件施加DC偏置电压; 设置在所述基板的区域上的热塑性材料层; 以及磁性物质层，其设置在所述基板的包括所述偏压线的区域的区域上，并粘附并由所述热塑性材料层支撑。 在该结构中，可以根据诸如晶体管的有源元件的振荡特性，以适当的形状和偏置线上的适当位置形成磁性物质层，并且磁性物质层吸收 有源元件的振荡，从而容易防止有源元件的振荡。 此外，由于磁性物质层设置在偏置线上，所以避免了由于使用现有技术的振荡防止电路而导致的集成电路器件的芯片面积的不必要的增加。

    Inductive structures for semiconductor integrated circuits
    6.
    发明授权
    Inductive structures for semiconductor integrated circuits 失效
    半导体集成电路的电感结构

    公开(公告)号：US5095357A

    公开(公告)日：1992-03-10

    申请号：US567170

    申请日：1990-08-14

    申请人： Naoto Andoh ,  Akira Inoue ,  Yasuharu Nakajima ,  Kazuhiko Nakahara

    发明人： Naoto Andoh ,  Akira Inoue ,  Yasuharu Nakajima ,  Kazuhiko Nakahara

    IPC分类号： H01L21/822 ,  H01F17/00 ,  H01F21/08 ,  H01F27/28 ,  H01L21/02 ,  H01L23/64 ,  H01L27/04

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F17/0033 ,  H01F21/08 ,  H01F27/2804 ,  H01L23/645 ,  H01F2017/004 ,  H01F2017/0046 ,  H01F2017/0086 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Inductive structures having low parasitic capacitances for direct integration in semiconductor integrated circuits. In one embodiment, a generally planar spiral winding is disposed on the surface of a substrate. An electrical connection to the internal end of the spiral is made through electrically conducting vias passing through the substrate. The spiral may be spaced from a substrate surface by a plurality of spaced apart electrically conductive posts having a staggered arrangement between adjacent windings of the spiral. A transformer includes two windings disposed on top of each other on a semiconductor substrate and separated by an electrically insulating film. The windings have a common central opening in which a magnetic material is disposed to improve the inductive coupling between the windings. The transformer may include two helical windings, one surrounding another, each formed with vias and electrical conductors, the inner winding being formed in and on a semiconductor substrate and the outer winding being formed on insulating films disposed on the substrate and extending through the films and substrate. A variable inductor includes inductively coupled spiral windings separated by an insulating film and a current control for controlling the current through one of the spirals and, thereby, the effective inductance of the other spiral.

    Information presentation system and in-vehicle apparatus
    7.
    发明授权
    Information presentation system and in-vehicle apparatus 有权
    信息呈现系统和车载设备

    公开(公告)号：US09037345B2

    公开(公告)日：2015-05-19

    申请号：US14001070

    申请日：2012-03-08

    申请人： Akira Inoue

    发明人： Akira Inoue

    IPC分类号： G06F3/14 ,  H04M1/725

    CPC分类号： G06F3/1423 ,  H04M1/7253 ,  H04M1/72577

    摘要： A mobile terminal displays a screen image provided by an image data which is produced. An in-vehicle apparatus is fixed to a vehicle or is mounted on the vehicle to be portable. The mobile terminal sends the image data to the in-vehicle apparatus through communication such that a vehicle display portion of the in-vehicle apparatus displays a screen image provided by the image data. In a case where a communication between the in-vehicle apparatus and the mobile terminal is established, when one of the mobile terminal or the in-vehicle apparatus, in which an input operation has been performed prior to the other of the mobile terminal or the in-vehicle apparatus, is in operation, only the one of the mobile terminal or the in-vehicle apparatus is operable.

    摘要翻译： 移动终端显示由所生成的图像数据提供的屏幕图像。 车载设备固定在车辆上或安装在车辆上以便携带。 移动终端通过通信将图像数据发送到车载设备，使得车载设备的车辆显示部分显示由图像数据提供的屏幕图像。 在建立车载设备与移动终端之间的通信的情况下，当移动终端或车载设备中的一个在移动终端或另一个移动终端之前进行了输入操作时 车载设备正在操作中，只有移动终端或车载设备中的一个可操作。