公开(公告)号：US09254548B2

公开(公告)日：2016-02-09

申请号：US13455448

申请日：2012-04-25

申请人： Yen-Chang Chao ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Yen-Chang Chao ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： B24B53/017 ,  B24D3/06 ,  B24D3/28 ,  B24D18/00

CPC分类号： B24B53/12 ,  B24B53/017 ,  B24D3/06 ,  B24D3/28 ,  B24D18/00

摘要： A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.

摘要翻译： 用于制造在化学机械抛光（CMP）工艺中使用的调节盘的方法包括在衬底上施加至少一种粘合剂的第一层; 在所述多个位置处在所述至少一个第一粘合剂的所述第一层上设置多个金刚石颗粒; 以及通过将衬底加热到​​升高的温度然后冷却衬底，将多个金刚石颗粒固定到衬底上。 设置在基板上的多个金刚石颗粒被配置为当在CMP工艺中使用调节盘时，提供高于50％的工作金刚石比例。

公开(公告)号：US09676114B2

公开(公告)日：2017-06-13

申请号：US13408327

申请日：2012-02-29

申请人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

发明人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

IPC分类号： B26D1/143 ,  B28D5/02 ,  B24D5/02 ,  B24D5/12 ,  B23D61/02 ,  B28D1/04 ,  B26D7/18 ,  B28D1/12

CPC分类号： B26D7/18 ,  B23D61/02 ,  B23D61/021 ,  B24D5/02 ,  B24D5/12 ,  B26D1/143 ,  B28D1/04 ,  B28D1/121 ,  B28D5/022 ,  Y10T83/0448 ,  Y10T83/9372

摘要： A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.

公开(公告)号：US20130228886A1

公开(公告)日：2013-09-05

申请号：US13409924

申请日：2012-03-01

申请人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/1464 ,  H01L27/14687

摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

摘要翻译： 公开了用于背面照明（BSI）图像传感器装置的方法和装置。 在包括感光二极管的基板上形成BSI传感器装置。 衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。 另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

公开(公告)号：US20120292639A1

公开(公告)日：2012-11-22

申请号：US13111732

申请日：2011-05-19

申请人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： H01L29/06 ,  H01L29/24 ,  H01L21/762

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

摘要翻译： 公开了一种制造半导体器件的半导体器件和方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供衬底并在衬底上形成电介质层。 该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层 活动层

公开(公告)号：US08247322B2

公开(公告)日：2012-08-21

申请号：US11680981

申请日：2007-03-01

申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/7684

摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

公开(公告)号：US07837841B2

公开(公告)日：2010-11-23

申请号：US11686504

申请日：2007-03-15

申请人： Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

IPC分类号： C25D5/00 ,  C25D5/18 ,  C25D17/00 ,  C25B15/00

CPC分类号： C25D17/001 ,  C25D17/007 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  Y10T428/16

摘要： Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.

摘要翻译： 具有辅助阴极的电化学电镀（ECP）装置，以产生均匀的电流密度。 用于电化学沉积的ECP设备包括具有用于在基底上电化学沉积金属的电解质浴的电化学电池。 主阴极和阳极设置在电解槽中以提供主电场。 衬底保持器组件保持连接阴极的半导体晶片。 辅助阴极设置在电化学电池外部以提供辅助电场，使得衬底保持器组件的中心区域处的磁通线密度基本上等于衬底保持器组件的圆周处的磁通密度。

公开(公告)号：US07803257B2

公开(公告)日：2010-09-28

申请号：US10971836

申请日：2004-10-22

申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

IPC分类号： C25D17/14 ,  C25D17/12

CPC分类号： H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

摘要翻译： 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

公开(公告)号：US20090127097A1

公开(公告)日：2009-05-21

申请号：US11941435

申请日：2007-11-16

申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C14/00

CPC分类号： C23C14/345 ,  C23C14/046 ,  H01L21/76862 ,  H01L21/76873

摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.

摘要翻译： 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

公开(公告)号：US07312149B2

公开(公告)日：2007-12-25

申请号：US10840095

申请日：2004-05-06

申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

IPC分类号： H01L21/44

CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

公开(公告)号：US20050275941A1

公开(公告)日：2005-12-15

申请号：US10854061

申请日：2004-05-26

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shih-Tzung Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shih-Tzung Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

IPC分类号： G02B23/00 ,  H01L21/768 ,  H01L21/82

CPC分类号： H01L21/7684 ,  H01L21/76877

摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

摘要翻译： 在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。 导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。 导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。