公开(公告)号：US07312149B2

公开(公告)日：2007-12-25

申请号：US10840095

申请日：2004-05-06

申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

IPC分类号： H01L21/44

CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

公开(公告)号：US20050250327A1

公开(公告)日：2005-11-10

申请号：US10840095

申请日：2004-05-06

申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

IPC分类号： C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288 ,  H01L21/44

CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

公开(公告)号：US07128821B2

公开(公告)日：2006-10-31

申请号：US10761477

申请日：2004-01-20

申请人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： C25D5/34 ,  C25F1/00

CPC分类号： H01L21/76843 ,  B24B37/042 ,  B24B37/046 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25F3/02 ,  H01L21/02068 ,  H01L21/32115 ,  H01L21/76865 ,  H01L21/76873

摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.

摘要翻译： 公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。 该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。 该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

公开(公告)号：US20050155869A1

公开(公告)日：2005-07-21

申请号：US10761477

申请日：2004-01-20

申请人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： B24B37/04 ,  C25D3/38 ,  C25D5/18 ,  C25D7/12 ,  C25F3/02 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  B23H3/00

CPC分类号： H01L21/76843 ,  B24B37/042 ,  B24B37/046 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25F3/02 ,  H01L21/02068 ,  H01L21/32115 ,  H01L21/76865 ,  H01L21/76873

摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.

摘要翻译： 公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。 该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。 该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

公开(公告)号：US20060055928A1

公开(公告)日：2006-03-16

申请号：US10942554

申请日：2004-09-15

申请人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

发明人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

IPC分类号： G01B11/00

CPC分类号： H01L22/34 ,  G01B21/042

摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

摘要翻译： 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时，激光束撞击目标点并释放到生产中。 如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

公开(公告)号：US20050236181A1

公开(公告)日：2005-10-27

申请号：US10917543

申请日：2004-08-12

申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.

摘要翻译： 公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。 该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。 还公开了具有至少一个无空隙通孔的互连结构。

公开(公告)号：US20070084730A1

公开(公告)日：2007-04-19

申请号：US11248176

申请日：2005-10-13

申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： C25D5/48

CPC分类号： C25D21/00 ,  C25D5/00 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

摘要翻译： 电镀设备和电镀工艺。 电镀装置包括电镀站和邻近电镀站的电镀后处理站。 电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。 后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

公开(公告)号：US07071100B2

公开(公告)日：2006-07-04

申请号：US10788912

申请日：2004-02-27

申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

公开(公告)号：US20050191855A1

公开(公告)日：2005-09-01

申请号：US10788912

申请日：2004-02-27

申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

公开(公告)号：US20070205516A1

公开(公告)日：2007-09-06

申请号：US11364088

申请日：2006-03-01

申请人： Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3146 ,  H01L21/31633 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

摘要翻译： 低k电介质层，半导体器件及其制造方法。 低k电介质层包括夹在两个低k电介质子层之间的硬化子层。 硬化的子层通过利用氢等离子体或惰性气体等离子体轰击下面的低k电介质子层的方法形成。 半导体器件包括覆盖衬底上的蚀刻停止层的低k电介质层，以及电连接到衬底的埋入电介质层和蚀刻停止层中的导电材料。