利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.039 秒)

    Gate height loss improvement for a transistor
    6.
    发明授权
    Gate height loss improvement for a transistor 有权
    晶体管的栅极高度损耗改善

    公开(公告)号：US08598028B2

    公开(公告)日：2013-12-03

    申请号：US13335771

    申请日：2011-12-22

    申请人： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

    发明人： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

    IPC分类号： H01L21/3205 ,  H01L21/20

    CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底的iso区域上形成第一栅极结构，并且在衬底的致密区域上形成第二栅极结构。 密集区域具有比iso区域更大的图案密度。 第一和第二栅极结构各自具有设置在其上的相应的硬掩模。 该方法包括从第一和第二栅极结构去除硬掩模。 从第二栅极结构去除硬掩模导致在第二栅极结构中形成开口。 该方法包括执行沉积过程，随后进行第一抛光工艺以在开口中形成牺牲部件。 该方法包括执行第二抛光工艺以去除牺牲部件以及第一和第二栅极结构的部分。

    GROUP III-V SOLAR CELL AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    GROUP III-V SOLAR CELL AND METHOD OF MANUFACTURING THE SAME 审中-公开
    III-V族太阳能电池及其制造方法

    公开(公告)号：US20110308607A1

    公开(公告)日：2011-12-22

    申请号：US13017221

    申请日：2011-01-31

    申请人： YEE-SHYI CHANG ,  Chi-Jen Liu

    发明人： YEE-SHYI CHANG ,  Chi-Jen Liu

    IPC分类号： H01L31/0376 ,  H01L31/0352

    CPC分类号： H01L31/076 ,  H01L31/0304 ,  H01L31/03762 ,  H01L31/202 ,  Y02E10/544 ,  Y02E10/548 ,  Y02P70/521

    摘要： A Group III-V solar cell and a manufacturing method thereof, wherein, three amorphous silicon layers are formed on a substrate, which includes a first type amorphous silicon layer, an intrinsic amorphous silicon layer, and a second type amorphous silicon layer. The lattice characteristics of amorphous silicon layer are utilized, and a Group III-V polycrystalline semiconductor layer is formed on said amorphous silicon layer, such that amorphous silicon and Group III-V material are able to perform photoelectric conversion simultaneously in raising photoelectric conversion efficiency of said Group III-V solar cell effectively by means of a direct energy gap of said Group III-V material.

    摘要翻译： III-V族太阳能电池及其制造方法，其特征在于，在包括第一非晶硅层，本征非晶硅层和第二非晶硅层的基板上形成三个非晶硅层。 利用非晶硅层的晶格特性，在所述非晶硅层上形成III-V族多晶半导体层，使得非晶硅和III-V族材料能够同时进行光电转换，提高光电转换效率 所述III-V族太阳能电池通过所述III-V族材料的直接能隙有效地进行。

    GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR
    9.
    发明申请
    GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR 有权
    栅极高度损失改善晶体管

    公开(公告)号：US20130164930A1

    公开(公告)日：2013-06-27

    申请号：US13335771

    申请日：2011-12-22

    申请人： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

    发明人： Che-Hao Tu ,  Chi-Jen Liu ,  Tzu-Chung Wang ,  Weilun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

    IPC分类号： H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底的iso区域上形成第一栅极结构，并且在衬底的致密区域上形成第二栅极结构。 密集区域具有比iso区域更大的图案密度。 第一和第二栅极结构各自具有设置在其上的相应的硬掩模。 该方法包括从第一和第二栅极结构去除硬掩模。 从第二栅极结构去除硬掩模导致在第二栅极结构中形成开口。 该方法包括执行沉积过程，随后进行第一抛光工艺以在开口中形成牺牲部件。 该方法包括执行第二抛光工艺以去除牺牲部件以及第一和第二栅极结构的部分。