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34 条记录 (耗时 0.035 秒)

    Interposer for recessed flip-chip package
    2.
    发明授权
    Interposer for recessed flip-chip package 有权
    插入式倒装芯片封装

    公开(公告)号：US06175158B1

    公开(公告)日：2001-01-16

    申请号：US09149803

    申请日：1998-09-08

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  Robert Charles Frye ,  King Lien Tai

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  Robert Charles Frye ,  King Lien Tai

    IPC分类号： H01L2348

    CPC分类号： H01L23/49833 ,  H01L23/49838 ,  H01L2224/16

    摘要： The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.

    摘要翻译： 该说明书描述了一种嵌入式芯片IC封装，其中IC芯片被结合到硅转换器，并且用于IC电源和接地互连的电源和接地层形成在转换器的分开的互连级上。 转换器的多电平互联能力允许交叉，并允许IC芯片的电源和接地引脚与信号I / O隔离，并且整合到进入下一个电路板级别的较少互连。 硅转换器和常规印刷线路板材料之间的热失配通过使用插入器来解决，该插入器本质上是将互连图案从转换器传送到印刷线路板的电镀通孔的球栅阵列。 插入件可以具有位于硅的CTE和板材料的CTE之间的热膨胀系数（CTE）的组成。 它还可以设置有用于额外的应力释放的孔或槽。

    Fabricating high-Q RF components
    5.
    发明授权
    Fabricating high-Q RF components 有权
    制造高Q射频元件

    公开(公告)号：US06232047B1

    公开(公告)日：2001-05-15

    申请号：US09261093

    申请日：1999-03-02

    申请人： Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

    发明人： Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

    IPC分类号： G03C500

    CPC分类号： H05K3/246 ,  H01P11/003 ,  H05K1/0242 ,  H05K3/146 ,  H05K2201/0317

    摘要： The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.

    摘要翻译： 该说明书描述了用于改善由厚膜糊技术形成的导电金属条的边缘敏锐度的方法。 实现了使用厚膜技术形成的条的体积特性的优点，同时利用在导电条的边缘处的薄膜修剪带克服了差的边缘限定的缺点。

    Multi-chip modules with isolated coupling between modules
    6.
    发明授权
    Multi-chip modules with isolated coupling between modules 失效
    模块间隔离耦合的多芯片模块

    公开(公告)号：US5747982A

    公开(公告)日：1998-05-05

    申请号：US761047

    申请日：1996-12-05

    申请人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

    发明人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

    IPC分类号： H01L25/16 ,  H05K1/02 ,  G05F5/00 ,  H03H7/00

    CPC分类号： H05K1/0256 ,  H01L25/162 ,  H05K1/0262 ,  H05K1/0274 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/1003 ,  Y10S323/902

    摘要： A silicon-on-silicon dual MCM apparatus comprising a printed circuit board having a voltage isolation boundary contained therein supporting a pair of multi-chip modules on either side of the voltage isolation boundary. The MCMs safely convey signals across the isolation boundary via discrete optical coupling means or the like. The optical coupling means allow safe and efficient conveyance of signals across the voltage isolation boundary enabling a designer to group high voltage components on one side of the boundary and low voltage components on the other side of the boundary. This obviates to a degree the need for multi-layered PCBs. A relatively large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog integrated circuits (ICs). Operational characteristics of the controller are verified after integration and are compared to the discrete version. High voltage isolation requirements, interference, and noise are all considered to determine the most critical portions of the dual MCM layout and design.

    摘要翻译： 一种硅上硅双MCM装置，包括其中包含电压隔离边界的印刷电路板，其在电压隔离边界的两侧支撑一对多芯片模块。 MCM通过离散光耦合装置等将信号安全地传送到隔离边界。 光耦合装置允许跨越电压隔离边界安全有效地传输信号，使得设计人员可以对边界一侧的高压部件和边界另一侧的低电压部件进行分组。 这在一定程度上消除了对多层PCB的需求。 通过倒装芯片模拟集成电路（IC）将相对大量的无源元件（电阻和电容器）集成到硅衬底中。 控制器的操作特性在集成后验证，并与离散版本进行比较。 高电压隔离要求，干扰和噪声都被认为是确定双MCM布局和设计的最关键部分。

    Miniaturized wide-band baluns for RF applications
    7.
    发明授权
    Miniaturized wide-band baluns for RF applications 有权

    公开(公告)号：US08803630B2

    公开(公告)日：2014-08-12

    申请号：US12579299

    申请日：2009-10-14

    申请人： Kai Liu ,  Robert Charles Frye

    发明人： Kai Liu ,  Robert Charles Frye

    IPC分类号： H03H7/42 ,  H01P3/08 ,  H01F17/00

    CPC分类号： H03H7/42 ,  H01F17/0013 ,  H03H7/1775 ,  Y10T29/4902 ,  Y10T29/49071

    摘要： A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.

    Semiconductor device and method of forming thin film capacitor
    9.
    发明授权
    Semiconductor device and method of forming thin film capacitor 有权
    半导体器件和薄膜电容器的形成方法

    公开(公告)号：US08111113B2

    公开(公告)日：2012-02-07

    申请号：US12705810

    申请日：2010-02-15

    申请人： Kai Liu ,  Robert Charles Frye

    发明人： Kai Liu ,  Robert Charles Frye

    IPC分类号： H03H7/00 ,  H01G4/06

    CPC分类号： H03H7/09 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H03H7/1708 ,  H03H7/1775 ,  Y10T29/4902

    摘要： A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.

    摘要翻译： 半导体器件具有形成在衬底上的第一线圈结构。 在与第一线圈结构相邻的衬底上形成第二线圈结构。 在与第二线圈结构相邻的衬底上形成第三线圈结构。 第一和第二线圈结构通过互感耦合，并且第二和第三线圈结构通过互感耦合。 第一，第二和第三线圈结构各自具有高于线圈结构的皮肤电流深度的高度，其被定义为电流减小到表面电流值的1 /（复数介电常数）的深度。 通过第一金属板，第一金属板上的电介质层和与第一金属板相对的第二和第三电隔离金属板，在半导体器件内形成薄膜电容器。 端子位于电容器的同一侧。

    Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
    10.
    发明申请
    Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) 有权
    在集成无源器件（IPD）中形成电容器和互连顶电极的方法

    公开(公告)号：US20100200951A1

    公开(公告)日：2010-08-12

    申请号：US12763386

    申请日：2010-04-20

    申请人： Yaojian Lin ,  Robert Charles Frye

    发明人： Yaojian Lin ,  Robert Charles Frye

    IPC分类号： H01L23/522

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

    摘要翻译： 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。