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30 条记录 (耗时 0.021 秒)

    Fabricating high-Q RF components
    1.
    发明授权
    Fabricating high-Q RF components 有权
    制造高Q射频元件

    公开(公告)号：US06232047B1

    公开(公告)日：2001-05-15

    申请号：US09261093

    申请日：1999-03-02

    申请人： Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

    发明人： Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

    IPC分类号： G03C500

    CPC分类号： H05K3/246 ,  H01P11/003 ,  H05K1/0242 ,  H05K3/146 ,  H05K2201/0317

    摘要： The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.

    摘要翻译： 该说明书描述了用于改善由厚膜糊技术形成的导电金属条的边缘敏锐度的方法。 实现了使用厚膜技术形成的条的体积特性的优点，同时利用在导电条的边缘处的薄膜修剪带克服了差的边缘限定的缺点。

    Interposer for recessed flip-chip package
    2.
    发明授权
    Interposer for recessed flip-chip package 有权
    插入式倒装芯片封装

    公开(公告)号：US06175158B1

    公开(公告)日：2001-01-16

    申请号：US09149803

    申请日：1998-09-08

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  Robert Charles Frye ,  King Lien Tai

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  Robert Charles Frye ,  King Lien Tai

    IPC分类号： H01L2348

    CPC分类号： H01L23/49833 ,  H01L23/49838 ,  H01L2224/16

    摘要： The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.

    摘要翻译： 该说明书描述了一种嵌入式芯片IC封装，其中IC芯片被结合到硅转换器，并且用于IC电源和接地互连的电源和接地层形成在转换器的分开的互连级上。 转换器的多电平互联能力允许交叉，并允许IC芯片的电源和接地引脚与信号I / O隔离，并且整合到进入下一个电路板级别的较少互连。 硅转换器和常规印刷线路板材料之间的热失配通过使用插入器来解决，该插入器本质上是将互连图案从转换器传送到印刷线路板的电镀通孔的球栅阵列。 插入件可以具有位于硅的CTE和板材料的CTE之间的热膨胀系数（CTE）的组成。 它还可以设置有用于额外的应力释放的孔或槽。

    Multi-chip modules with isolated coupling between modules
    3.
    发明授权
    Multi-chip modules with isolated coupling between modules 失效
    模块间隔离耦合的多芯片模块

    公开(公告)号：US5747982A

    公开(公告)日：1998-05-05

    申请号：US761047

    申请日：1996-12-05

    申请人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

    发明人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

    IPC分类号： H01L25/16 ,  H05K1/02 ,  G05F5/00 ,  H03H7/00

    CPC分类号： H05K1/0256 ,  H01L25/162 ,  H05K1/0262 ,  H05K1/0274 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/1003 ,  Y10S323/902

    摘要： A silicon-on-silicon dual MCM apparatus comprising a printed circuit board having a voltage isolation boundary contained therein supporting a pair of multi-chip modules on either side of the voltage isolation boundary. The MCMs safely convey signals across the isolation boundary via discrete optical coupling means or the like. The optical coupling means allow safe and efficient conveyance of signals across the voltage isolation boundary enabling a designer to group high voltage components on one side of the boundary and low voltage components on the other side of the boundary. This obviates to a degree the need for multi-layered PCBs. A relatively large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog integrated circuits (ICs). Operational characteristics of the controller are verified after integration and are compared to the discrete version. High voltage isolation requirements, interference, and noise are all considered to determine the most critical portions of the dual MCM layout and design.

    摘要翻译： 一种硅上硅双MCM装置，包括其中包含电压隔离边界的印刷电路板，其在电压隔离边界的两侧支撑一对多芯片模块。 MCM通过离散光耦合装置等将信号安全地传送到隔离边界。 光耦合装置允许跨越电压隔离边界安全有效地传输信号，使得设计人员可以对边界一侧的高压部件和边界另一侧的低电压部件进行分组。 这在一定程度上消除了对多层PCB的需求。 通过倒装芯片模拟集成电路（IC）将相对大量的无源元件（电阻和电容器）集成到硅衬底中。 控制器的操作特性在集成后验证，并与离散版本进行比较。 高电压隔离要求，干扰和噪声都被认为是确定双MCM布局和设计的最关键部分。

    Methods and apparatus for testing integrated circuits
    8.
    发明授权
    Methods and apparatus for testing integrated circuits 有权
    集成电路测试方法和设备

    公开(公告)号：US06560735B1

    公开(公告)日：2003-05-06

    申请号：US09366388

    申请日：1999-08-03

    申请人： Louis Nelson Ahlquist ,  Yinon Degani ,  Jericho J. Jacala ,  Dean Paul Kossives ,  King Lien Tai

    发明人： Louis Nelson Ahlquist ,  Yinon Degani ,  Jericho J. Jacala ,  Dean Paul Kossives ,  King Lien Tai

    IPC分类号： G01R3128

    CPC分类号： G01R31/2853

    摘要： The specification describes an IC test apparatus having a test bed with sockets adapted to engage arrays of I/O solder balls/bumps on the IC chip. In one embodiment the sockets are provided with through holes to interconnect the solder bumps to the next board level with minimum electrical path length thereby reducing parasitic capacitive coupling. In another embodiment the sockets in the test bed are formed by intersecting V-grooves. If pairs of intersecting V-grooves are used, pyramid shaped features are produced at the bottom of each socket. Both the sharp edges formed by the intersecting V-grooves and the pyramid provide contact enhancement between the solder bumps and the test bed. The test bed can be made as a universal blank for a given solder bump pitch. The desired test circuit is formed at the next board level.

    摘要翻译： 本说明书描述了一种具有测试台的IC测试装置，其具有适于接合IC芯片上的I / O焊球/凸起阵列的插座。 在一个实施例中，插座设置有通孔，以将焊料凸块互连到具有最小电路长度的下一个电路板级，从而减少寄生电容耦合。 在另一个实施例中，试验台中的插座由V形槽相交形成。 如果使用成对的相交的V形槽，则在每个插座的底部产生金字塔形特征。 由相交的V形槽和金字塔形成的锐利边缘都提供焊料凸块和试验台之间的接触增强。 测试台可以作为给定焊料凸块间距的通用坯料。 所需的测试电路在下一个电路板级形成。

    Packaging silicon on silicon multichip modules
    9.
    发明授权
    Packaging silicon on silicon multichip modules 失效
    包装硅多芯片模块

    公开(公告)号：US06369444B1

    公开(公告)日：2002-04-09

    申请号：US09081448

    申请日：1998-05-19

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  King Lien Tai

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  King Lien Tai

    IPC分类号： H01L2334

    CPC分类号： H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15151 ,  H01L2924/15321

    摘要： The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.

    摘要翻译： 该规范描述了硅上硅多芯片模块的互连组件。 硅上硅MCM安装在具有基本上与硅的CTE匹配的热膨胀系数（CTE）的环氧树脂/玻璃层压板上。 在优选实施例中，组件是具有卡边缘连接器的PC卡，即没有固定的焊料层间互连，使得可以修改包含卡的环氧树脂层压体的CTE，而不考虑与母板的潜在不匹配。