摘要:
The specification describes an MCM package which contains both a digital MCM and an RF MCM in a stacked configuration. The package contains means for isolating RF signals from digital signals. In one case the digital MCM substrate is attached to the system substrate and the RF MCM substrate is attached to the digital MCM substrate. Solder bumps are used for attachment in an arrangement resembling a BGA. For high density packages, at least the digital MCM comprises stacked IC chips. In the embodiment with the RF MCM substrate on the top of the stack, Passive Through Interconnections (PTIs) are made through the digital MCM substrate, and electrically isolated therefrom. The passive through interconnections are made through the solder bumps between boards and interconnected using a passive (with respect to the digital MCM board) through hole. Both the RF ground and the RF input can be isolated using PTIs. For additional isolation, the solder bumps comprising the PTIs are shielded with a Faraday cage. The Faraday cage comprises an array of solder bumps surrounding the solder bump RF conductors.
摘要:
The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.
摘要:
The specification describes a recessed chip MCM package with integrated electromagnetic shielding. The surfaces of the cavity which houses the IC devices are coated with metallization. The normally exposed top and side surfaces of the MCM package are also metallized. A solder wall is provided on the interconnect PCB which seals the gap between the MCM tile and the PCB interconnect substrate. The solder wall can be formed using standard solder bump technology, and the seal between the MCM and the PCB may be made during the same reflow operation that is used to flip-chip bond the MCM tile to the PCB.
摘要:
The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.
摘要翻译:该说明书描述了IC芯片与硅中间互连基板(IIS)接合的高密度I / O IC封装,并且IIS被引线接合到印刷电路板。 这种线接技术与高密度I / O IC芯片的结合导致低成本,高可靠性,最先进的IC封装。
摘要:
A technique for monitoring the drawdown zone of an optical fiber preform is disclosed. The technique involves detecting the caustic rays emanating from the drawdown zone. Analysis of these rays allows one to determine the geometric properties of both the drawdown zone and the resultant optical fiber. In addition, detailed information concerning the index of refraction distribution in the fiber may be obtained. The process is amenable to realtime applications during the drawing of an optical fiber.
摘要:
The specification describes interconnection strategies for micro-electronic machined mechanical systems (MEMS). Typical MEMS device array comprise a large number of individual mechanical devices each electrically driven by multi-chip modules (MCMs). High density interconnection is achieved by mounting the MCMs mounted on both sides of a system interconnection substrate. Overall interconnection length is reduced by locating the MCMs in a common circuit driving a given mechanical element on opposite sides of the system interconnection substrate and interconnecting them using vias through the substrate. Rapid replacement/repair is facilitated by mounted all active elements in sockets using contact pin arrays for electrical connections. In service reliability is obtained by providing spare sockets for redundant MCMs.
摘要:
The specification describes a method for dispensing IC chips from a chip carrier tape for a flip-chip assembly operation. In a conventional assembly operation, the solder bumped side of the chip is the top side of the chip as loaded on the tape, and is normally the side of the chip that engages the head of the pick tool. For flip-chip assembly it is necessary to invert the chip for solder bonding to an interconnect substrate. In the technique of the invention, the chip carrier tape is inverted and inserted into the dispensing machine upside down. The IC chips are then ejected through the back of the tape instead of being lifted from the from of the tape. In this way the pick tool head engages the back side of the solder bumped chip and the chip is in the proper orientation for flip-chip placement and bonding on the interconnect substrate. Carrier tapes designed for through-tape dispensing are also disclosed.
摘要:
The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.
摘要:
The bottom and side surfaces of an electronic device, such as an integrated circuit chip or a multichip assembly, are surrounded by a soft gel medium. The gel medium is laterally confined by a rigid plastic rim that is epoxy-bonded in place along its perimeter. A plate, made of plastic or metal, can be attached to the top surface of the rim, in order to provide a cover for the package.
摘要:
The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.