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    Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells
    1.
    发明申请
    Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells 有权
    用于多级单元（MLC）存储单元的非顺序编码方案

    公开(公告)号：US20120243311A1

    公开(公告)日：2012-09-27

    申请号：US13070021

    申请日：2011-03-23

    申请人： Yiran Chen ,  Dadi Setiadi ,  Patrick J. Ryan

    发明人： Yiran Chen ,  Dadi Setiadi ,  Patrick J. Ryan

    IPC分类号： G11C16/04 ,  G11C11/14

    CPC分类号： G11C11/161 ,  G11C7/1006 ,  G11C11/5607 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5648

    摘要： Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

    摘要翻译： 用于管理多层单元（MLC）存储单元阵列的装置和方法。 根据各种实施例，选择非顺序编码方案，其相对于与所述多个存储器单元中的每一个相关联的写入功率，将所选择的MLC存储器单元的多个可用物理状态中的每一个分配给不同的多位逻辑值 物理状态 相关于所选择的非顺序编码方案，数据被写入所选择的MLC存储器单元。 在一些实施例中，MLC存储器单元包括自旋转矩传递随机存取存储器（STRAM）存储器单元。 在其他实施例中，MLC存储器单元包括MLC闪存单元。

    Non-sequential encoding scheme for multi-level cell (MLC) memory cells
    2.
    发明授权
    Non-sequential encoding scheme for multi-level cell (MLC) memory cells 有权
    多级单元（MLC）存储单元的非顺序编码方案

    公开(公告)号：US08942035B2

    公开(公告)日：2015-01-27

    申请号：US13070021

    申请日：2011-03-23

    申请人： Yiran Chen ,  Dadi Setiadi ,  Patrick J. Ryan

    发明人： Yiran Chen ,  Dadi Setiadi ,  Patrick J. Ryan

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/16 ,  G11C7/10 ,  G11C11/56

    CPC分类号： G11C11/161 ,  G11C7/1006 ,  G11C11/5607 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5648

    摘要： Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

    摘要翻译： 用于管理多层单元（MLC）存储单元阵列的装置和方法。 根据各种实施例，选择非顺序编码方案，其相对于与所述多个存储器单元中的每一个相关联的写入功率，将所选择的MLC存储器单元的多个可用物理状态中的每一个分配给不同的多位逻辑值 物理状态 相关于所选择的非顺序编码方案，数据被写入所选择的MLC存储器单元。 在一些实施例中，MLC存储器单元包括自旋转矩传递随机存取存储器（STRAM）存储器单元。 在其他实施例中，MLC存储器单元包括MLC闪存单元。

    Defective Bit Scheme for Multi-Layer Integrated Memory Device
    3.
    发明申请
    Defective Bit Scheme for Multi-Layer Integrated Memory Device 有权
    多层集成存储器件缺陷位方案

    公开(公告)号：US20110007588A1

    公开(公告)日：2011-01-13

    申请号：US12502194

    申请日：2009-07-13

    申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

    发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C15/00

    CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

    摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

    摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

    Defective bit scheme for multi-layer integrated memory device
    4.
    发明授权
    Defective bit scheme for multi-layer integrated memory device 有权
    多层集成存储器件的不良位方案

    公开(公告)号：US07936622B2

    公开(公告)日：2011-05-03

    申请号：US12502194

    申请日：2009-07-13

    申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

    发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

    IPC分类号： G11C29/00

    CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

    摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

    摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

    PIPELINED MEMORY ACCESS METHOD AND ARCHITECTURE THEREFORE
    5.
    发明申请
    PIPELINED MEMORY ACCESS METHOD AND ARCHITECTURE THEREFORE 审中-公开
    管道存储器访问方法和架构

    公开(公告)号：US20100037020A1

    公开(公告)日：2010-02-11

    申请号：US12200118

    申请日：2008-08-28

    申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

    发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1039 ,  G11C8/10 ,  G11C8/18

    摘要： A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs.

    摘要翻译： 一种用于访问存储器阵列的存储器阵列和方法，包括：从相关数据相关的主机接收地址; 基于从所述主机接收的地址访问第一模块，其中访问所述第一模块包括：解码所述第一模块的地址; 基于第一模块的解码地址启用字线，并感测第一模块的解码地址处的一个或多个位的内容; 并输出关于第一模块的信息; 以及基于从所述主机接收的地址访问第二模块，其中访问所述第二模块包括：对所述第二模块的地址进行解码; 基于第二模块的解码地址启用字线，并感测第二模块的解码地址处的一个或多个位的内容; 以及输出关于第二模块的信息，其中对第二模块的地址进行解码的步骤在基于第一模块的解码地址启用字线的步骤并且感测解码地址处的一个或多个位的内容的步骤 第一个模块发生。

    Generic non-volatile service layer
    6.
    发明授权
    Generic non-volatile service layer 有权
    通用非易失性服务层

    公开(公告)号：US07966581B2

    公开(公告)日：2011-06-21

    申请号：US12252564

    申请日：2008-10-16

    申请人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

    发明人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/14

    摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

    摘要翻译： 在电子设备中构建和操作集成电路的方法和装置。 在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。 通用服务层被重新配置为集成电路的永久性非测试功能组件。

    GENERIC NON-VOLATILE SERVICE LAYER
    7.
    发明申请
    GENERIC NON-VOLATILE SERVICE LAYER 有权
    一般非易失性服务层

    公开(公告)号：US20100100857A1

    公开(公告)日：2010-04-22

    申请号：US12252564

    申请日：2008-10-16

    申请人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

    发明人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/14

    摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

    摘要翻译： 在电子设备中构建和操作集成电路的方法和装置。 在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。 通用服务层被重新配置为集成电路的永久性非测试功能组件。

    Vertical transistor with hardening implatation
    8.
    发明授权
    Vertical transistor with hardening implatation 有权
    垂直晶体管与硬化插入

    公开(公告)号：US08617952B2

    公开(公告)日：2013-12-31

    申请号：US12891966

    申请日：2010-09-28

    申请人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

    发明人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

    IPC分类号： H01L21/336

    CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

    摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

    摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。