公开(公告)号：US06307665B1

公开(公告)日：2001-10-23

申请号：US09273758

申请日：1999-03-22

Applicant: Yong-hoon Kim ,  Hang-woo Lee

Inventor： Yong-hoon Kim ,  Hang-woo Lee

IPC: G02F133

CPC classification number: G02F1/332 ,  G02F1/0316 ,  G02F1/11 ,  G02F1/113

Abstract: An acousto-optic modulator including an ultrasonic medium for controlling light from an optical source through diffraction, two transducers each having one electrode formed on one side thereof, the electrodes being for generating an acousto-elastic wave, and a conductive adhesive layer interposed between the ultrasonic medium and each of the sides of the transducers opposite to the sides on which the electrodes are installed, in order to adhere each of the transducers to the ultrasonic medium.

Abstract translation: 一种声光调制器，包括用于通过衍射控制来自光源的光的超声波介质，两个换能器，每个换能器的一侧形成有一个电极，所述电极用于产生声弹性波，以及导电粘合剂层， 超声波介质和传感器的与安装有电极的侧面相对的侧面，以便将每个换能器粘附到超声波介质上。

公开(公告)号：US5900966A

公开(公告)日：1999-05-04

申请号：US911700

申请日：1997-08-15

Applicant: Yong-hoon Kim ,  Hang-woo Lee

Inventor： Yong-hoon Kim ,  Hang-woo Lee

IPC: G02F1/03 ,  G02F1/11 ,  G02F1/33

CPC classification number: G02F1/332 ,  G02F1/0316 ,  G02F1/11 ,  G02F1/113

Abstract: An acousto-optic modulator having an ultrasonic medium for controlling light from a light source by diffracting the light and a transducer portion having electrodes for generating an acoustic wave in the ultrasonic medium, wherein the transducer portion includes two transducers each having an electrode. The AOM is provided with two electrodes by using two transducers, thereby facilitating impedance matching with a driver. The two transducers may be installed so that their polarization directions are opposite to each other, thereby obtaining maximum power transfer to the ultrasonic medium.

Abstract translation: 一种声光调制器，其具有用于通过衍射光来控制来自光源的光的超声介质和具有用于在超声波介质中产生声波的电极的换能器部分，其中，所述换能器部分包括两个具有电极的换能器。 通过使用两个换能器，AOM设置有两个电极，从而有助于与驱动器的阻抗匹配。 可以安装两个换能器使得它们的偏振方向彼此相反，从而获得对超声介质的最大功率传递。

公开(公告)号：US06333129B2

公开(公告)日：2001-12-25

申请号：US09295352

申请日：1999-04-21

Applicant: Yong-hoon Kim ,  Jin-hong Park

Inventor： Yong-hoon Kim ,  Jin-hong Park

IPC: G03F900

CPC classification number: G03F1/29

Abstract: A method of fabricating a phase shift mask is provided in which light shield film patterns for setting a phase shift region and a phase non-shift region are simultaneously formed on a substrate. A groove is formed in the substrate set as the phase shift region. The light shield film pattern, which contacts the groove and is formed on a region of the substrate set as the phase non-shift region, is removed. A phase shift layer can be formed between the substrate and the light shield film pattern. In this case, regions set by the light shield film pattern become opposite to when the phase shift layer is not formed. That is, a phase shift region is changed into a phase non-shift region, and the phase non-shift region is changed into the phase shift region. As described above, the phase shift region and the phase non-shift region are simultaneously set when the light shield film pattern is formed, thus preventing the position of the phase shift or non-shift region from being shifted due to sequential formation of the phase shift and non-shift regions.

Abstract translation: 提供一种制造相移掩模的方法，其中在衬底上同时形成用于设置相移区域和相位非移位区域的光屏蔽膜图案。 在衬底组中形成有作为相移区域的沟槽。 除去接触凹槽并形成在作为相位非移位区域的基板的区域上的遮光膜图案。 可以在基板和遮光膜图案之间形成相移层。 在这种情况下，由遮光膜图案设定的区域与没有形成相移层时相反。 也就是说，相移区域被改变为相位非移位区域，并且相位非移位区域变为相移区域。 如上所述，当形成遮光膜图形时，相移区域和相位非移位区域被同时设置，从而防止相移或非移位区域的位置由于相位的顺序形成而偏移 移位和非移位区域。

公开(公告)号：US06296975B1

公开(公告)日：2001-10-02

申请号：US09426762

申请日：1999-10-26

Applicant: Seong-yong Moon ,  Yong-hoon Kim ,  Kwang-soo No

Inventor： Seong-yong Moon ,  Yong-hoon Kim ,  Kwang-soo No

IPC: G03F900

CPC classification number: G03F1/54

Abstract: A photo mask of a semiconductor device includes a transmission preventing layer formed of a molybdenum alloy, which is a solid solution of a metal atom such as chrome in molybdenum, on a light transmitting substrate. Also, the molybdenum alloy may be a molybdenum vanadium alloy, a molybdenum niobium alloy, a molybdenum tantalum alloy, or a molybdenum tungsten alloy, which is a solid solution of vanadium, niobium, tantalum, or tungsten in molybdenum, respectively. The photo mask provides high resolution during a photolithography process by obtaining a thinner transmission preventing layer.

Abstract translation: 半导体器件的光掩模包括由钼合金形成的防透光层，其是钼等金属原子的固溶体在透光性基板上。 此外，钼合金可以分别是钼中的钒，铌，钽或钨的固溶体的钼钒合金，钼铌合金，钼钽合金或钼钨合金。 光掩模通过获得较薄的防止传播层在光刻过程中提供高分辨率。

公开(公告)号：US09570383B2

公开(公告)日：2017-02-14

申请号：US14746247

申请日：2015-06-22

Applicant: Jin-Kyung Kim ,  Yong-hoon Kim ,  Seong-Ho Shin

Inventor： Jin-Kyung Kim ,  Yong-hoon Kim ,  Seong-Ho Shin

IPC: H01L23/02 ,  H01L23/498 ,  H05K1/18 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/09218 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.

Abstract translation: 提供半导体封装，模块基板和具有该半导体封装的半导体封装模块。 半导体封装模块包括在其上表面上设置有多个信号线的模块基板，设置在模块基板上的封装基板，设置在封装基板的一个表面上的半导体芯片，以及设置在多个外部连接端子 在封装衬底的另一个表面上。

公开(公告)号：US08587096B2

公开(公告)日：2013-11-19

申请号：US13172174

申请日：2011-06-29

Applicant: Yong-hoon Kim ,  Hee-seok Lee ,  Jin-Ha Jeong ,  Ji-hyun Lee

Inventor： Yong-hoon Kim ,  Hee-seok Lee ,  Jin-Ha Jeong ,  Ji-hyun Lee

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0233 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract translation: 示例实施例涉及半导体器件。 半导体器件可以包括第一半导体芯片，其包括半导体衬底，穿透半导体衬底的第一通孔，堆叠在第一半导体芯片的一个平面上的第二半导体芯片，以及覆盖第一半导体衬底的至少一部分的屏蔽层 和/或第二半导体芯片，并且电连接到第一通孔。

公开(公告)号：US07547940B2

公开(公告)日：2009-06-16

申请号：US11623829

申请日：2007-01-17

Applicant: Yong-hoon Kim

Inventor： Yong-hoon Kim

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11519

Abstract: Non-volatile memory devices according to embodiments of the present invention include an EEPROM transistor in a first portion of a semiconductor substrate, an access transistor in a second portion of the semiconductor substrate and an erase transistor in a third portion of the semiconductor substrate. The second portion of the semiconductor substrate extends adjacent a first side of the first portion of the semiconductor substrate and the third portion of the semiconductor substrate extends adjacent a second side of the first portion of the semiconductor substrate. The first and second sides of the first portion of the semiconductor substrate may be opposite sides of the first portion of the semiconductor substrate. The access transistor has a first source/drain terminal electrically connected to a first source/drain terminal of the EEPROM transistor and the erase transistor has a first source/drain terminal electrically connected to a second source/drain terminal of the access transistor.

Abstract translation: 根据本发明的实施例的非易失性存储器件包括在半导体衬底的第一部分中的EEPROM晶体管，半导体衬底的第二部分中的存取晶体管和半导体衬底的第三部分中的擦除晶体管。 半导体衬底的第二部分在半导体衬底的第一部分的第一侧附近延伸，并且半导体衬底的第三部分相邻于半导体衬底的第一部分的第二侧延伸。 半导体衬底的第一部分的第一和第二侧可以是半导体衬底的第一部分的相对侧。 存取晶体管具有电连接到EEPROM晶体管的第一源极/漏极端子的第一源极/漏极端子，并且擦除晶体管具有电连接到存取晶体管的第二源极/漏极端子的第一源极/漏极端子。

公开(公告)号：US08791559B2

公开(公告)日：2014-07-29

申请号：US13604301

申请日：2012-09-05

Applicant: Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

Inventor： Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/50

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/1301 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

Abstract translation: 提供了一种封装结构封装的半导体封装，减少了封装的整体厚度，并简化了布线路径的设计复杂性。 所述封装包括：第一封装，包括第一基板和安装在其上的第一半导体芯片部分;第二封装，设置在所述第一封装上，并且包括第二基板和安装在其上的第二半导体芯片部分;以及连接部件， 底物。 第二半导体芯片部分包括至少一个半导体芯片，其包括对应于一个通道的一组芯片焊盘，并且该组芯片焊盘集中在半导体芯片的第一边缘上。 对应于一个通道的知识产权核心形成在第一半导体芯片部分的边缘上，并且IP核心对应于芯片组集中的边缘。

公开(公告)号：US20110304015A1

公开(公告)日：2011-12-15

申请号：US13115431

申请日：2011-05-25

Applicant: Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

Inventor： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract translation: 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。

公开(公告)号：US08664751B2

公开(公告)日：2014-03-04

申请号：US13115431

申请日：2011-05-25

Applicant: Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

Inventor： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract translation: 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。