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公开(公告)号：US20110132546A1
公开(公告)日：2011-06-09
申请号：US12659029
申请日：2010-02-23
申请人： Yoong Oh , Dek Gin Yang
发明人： Yoong Oh , Dek Gin Yang
CPC分类号： B32B38/1816 , B32B38/0004 , B32B38/145 , B32B39/00 , B32B2457/08 , H05K3/00 , H05K3/40 , H05K3/46
摘要： Disclosed is an apparatus for manufacturing a printed circuit board. The apparatus for manufacturing the printed circuit board includes: a supplier for supplying a substrate of a sheet type; a first printer for printing paste on the substrate supplied from the supplier to thereby form preliminary bumps; a provisional dryer which is arranged on one side of the first printer and provisional-dries the preliminary bumps; a second printer which is arranged on one side of the provisional dryer to be in series to the first printer and prints paste on the preliminary bumps; a dryer which is arranged on one side of the second printer and dries and cures the preliminary bumps to thereby form bumps; and a penetrator which is arranged on one side of the dryer, and allows the bump to pass through prepreg and bonds the prepreg and the substrate together.
摘要翻译： 公开了一种印刷电路板的制造装置。 用于制造印刷电路板的装置包括：用于供应片状基板的供应商; 第一打印机，用于在从供应商供应的基板上印刷浆料，从而形成初步凸块; 临时干燥器，布置在第一打印机的一侧并对初步凸块进行暂时干燥; 第二打印机，其布置在所述临时干衣机的一侧以与所述第一打印机串联，并且在所述预备凸块上印刷浆料; 布置在第二打印机的一侧的干衣机，干燥并固化预备凸块从而形成凸块; 以及布置在干燥器的一侧的穿透器，并且允许凸块穿过预浸料并将预浸料和基材粘合在一起。
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公开(公告)号：US09060458B2
公开(公告)日：2015-06-16
申请号：US13137352
申请日：2011-08-08
申请人： Yoong Oh , Cheol Ho Choi
发明人： Yoong Oh , Cheol Ho Choi
CPC分类号： H05K3/4652 , H05K2203/0733 , H05K2203/1189 , Y10T29/49155
摘要： A method for manufacturing a multi-layer printed circuit board includes: forming first bumps on one surface of a first copper layer at a predetermined interval; providing, on the first copper layer, an insulating layer through which the first bumps are penetrating; stacking a second copper layer on a top of the insulating layer; forming circuits by patterning the first copper layer and the second copper layer; laminating insulating films on top and bottom surfaces of the insulating layer on which the circuits have been formed; forming second bumps on one surface of a third copper layer and of a fourth copper layer at a predetermined interval; and stacking the third copper layer and fourth copper layer, provided with the second bumps, on the top and bottom surfaces of the insulating films.
摘要翻译： 制造多层印刷电路板的方法包括：以预定间隔在第一铜层的一个表面上形成第一凸块; 在所述第一铜层上提供绝缘层，所述第一凸块穿过所述绝缘层; 在绝缘层的顶部堆叠第二铜层; 通过图案化第一铜层和第二铜层来形成电路; 在其上形成有电路的绝缘层的顶表面和底表面上层压绝缘膜; 在第三铜层和第四铜层的一个表面上以预定间隔形成第二凸起; 并且在绝缘膜的顶表面和底表面上堆叠设置有第二凸起的第三铜层和第四铜层。
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3.发明申请公开(公告)号：US20080283288A1
公开(公告)日：2008-11-20
申请号：US12219381
申请日：2008-07-21
申请人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
发明人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
IPC分类号： H05K1/11
CPC分类号： H05K3/462 , H01R12/523 , H05K3/4069 , H05K3/4647 , H05K3/4652 , H05K2201/0355 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2203/0353 , Y10T29/49155
摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.
摘要翻译： 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于糊状凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。
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4.发明授权公开(公告)号：US07973248B2
公开(公告)日：2011-07-05
申请号：US12219381
申请日：2008-07-21
申请人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
发明人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
CPC分类号： H05K3/462 , H01R12/523 , H05K3/4069 , H05K3/4647 , H05K3/4652 , H05K2201/0355 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2203/0353 , Y10T29/49155
摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.
摘要翻译： 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于粘贴凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。
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5.发明授权Method of manufacturing package substrate with fine circuit pattern using anodic oxidation 失效使用阳极氧化制造具有精细电路图案的封装衬底的方法公开(公告)号：US07169707B2
公开(公告)日：2007-01-30
申请号：US11011401
申请日：2004-12-13
申请人： Duck Young Maeng , Byung Kook Sun , Tae Hoon Kim , Jee Soo Mok , Jong Suk Bae , Yoong Oh , Chang-Kyu Song , Suk-Hyeon Cho
发明人： Duck Young Maeng , Byung Kook Sun , Tae Hoon Kim , Jee Soo Mok , Jong Suk Bae , Yoong Oh , Chang-Kyu Song , Suk-Hyeon Cho
IPC分类号： H01L21/302
CPC分类号： H01L21/486 , H01L23/142 , H01L2924/0002 , H05K3/205 , H05K3/207 , H05K3/4614 , H05K3/4617 , H05K3/4647 , H05K2203/0152 , H05K2203/0315 , H01L2924/00
摘要： Disclosed herein is a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. By anodizing a metal core which is opened through a masking process, oxidation layers are formed in open areas of the metal core to insulate portions of circuit pattern from each other. Further, by electroplating portions provided between the oxidation layers with copper or filling conductive paste between the oxidation layers using a screen, a package substrate having a fine circuit pattern is achieved.
摘要翻译： 本文公开了使用阳极氧化制造具有精细电路图案的封装衬底的方法。 通过对通过掩模工艺开放的金属芯进行阳极氧化，在金属芯的开放区域中形成氧化层，以使电路图案的部分彼此绝缘。 此外，通过使用屏幕将设置在氧化层之间的电镀部分用铜或在氧化层之间填充导电浆料，实现了具有精细电路图案的封装衬底。
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公开(公告)号：US08151446B2
公开(公告)日：2012-04-10
申请号：US12076223
申请日：2008-03-14
申请人： Jee-Soo Mok , Je-Gwang Yoo , Yoong Oh , Jong-Seok Bae , Chang-Sup Ryu
发明人： Jee-Soo Mok , Je-Gwang Yoo , Yoong Oh , Jong-Seok Bae , Chang-Sup Ryu
IPC分类号： B23P19/04
CPC分类号： H05K3/4647 , B29C43/28 , B29C43/46 , H05K3/4069 , H05K2203/0143 , H05K2203/1189 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/53126 , Y10T29/53178 , Y10T29/53183 , Y10T29/53187
摘要： An apparatus for manufacturing a printed circuit board that uses conductive bumps to interconnect layers includes: a conveyor unit, which is configured to transport a board that has the conductive bumps formed on one side; an upper roller and a lower roller, which press the board and an insulator together; an elastic coating layer, formed on a surface of the upper roller; and a cleaning device, which removes impurities from a surface of the elastic coating layer. The apparatus does not require a separate device for performing a cushioning function and a detaching function between the bumps and the rollers, and the rollers can be kept clean using a cleaning device.
摘要翻译： 用于制造使用导电凸块以互连层的印刷电路板的装置包括：输送单元，其被配置为输送在一侧形成有导电凸块的板; 上辊和下辊，将板和绝缘体压在一起; 形成在上辊的表面上的弹性涂层; 以及从弹性涂层的表面除去杂质的清洗装置。 该装置不需要用于执行缓冲功能和凸块和辊之间的分离功能的单独装置，并且可以使用清洁装置将辊保持清洁。
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公开(公告)号：US20120030942A1
公开(公告)日：2012-02-09
申请号：US13137352
申请日：2011-08-08
申请人： Yoong Oh , Cheol Ho Choi
发明人： Yoong Oh , Cheol Ho Choi
IPC分类号： H05K3/10
CPC分类号： H05K3/4652 , H05K2203/0733 , H05K2203/1189 , Y10T29/49155
摘要： Disclosed herein is a method for manufacturing a multi-layer printed circuit board. The method for manufacturing the multi-layer printed circuit board according to an exemplary embodiment of the present invention includes manufacturing a core substrate on which circuit patterns are formed by patterning copper clads on both sides thereof; laminating insulating films on top and bottom surfaces of the core substrate; and stacking the copper clads provided with bumps on the top and bottom surfaces of the core substrate, respectively, on which the insulating films are laminated.
摘要翻译： 本文公开了一种制造多层印刷电路板的方法。 根据本发明的示例性实施例的制造多层印刷电路板的方法包括通过在其两侧构图铜包层来制造其上形成有电路图案的芯基板; 在芯基板的顶表面和底表面上层压绝缘膜; 并且分别在其上层叠有绝缘膜的芯基板的顶表面和底表面上堆叠设置有凸块的铜包层。
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8.发明申请公开(公告)号：US20070107934A1
公开(公告)日：2007-05-17
申请号：US11598140
申请日：2006-11-13
申请人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
发明人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
CPC分类号： H05K3/462 , H01R12/523 , H05K3/4069 , H05K3/4647 , H05K3/4652 , H05K2201/0355 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2203/0353 , Y10T29/49155
摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a printed circuit board using paste bumps, comprising: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.
摘要翻译： 公开了一种使用糊状凸块的印刷电路板及其制造方法。 利用使用糊状凸块的印刷电路板的制造方法，其特征在于，包括：（a）对芯板进行穿孔以形成至少一个通孔，（b）通过填充电镀填充所述至少一个通孔并形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路， 可以通过增加镀层芯板的BVH的强度来实现层IVH结构，由于并行处理和集体堆叠，可以减少制造时间，由于粘贴凸块的铜箔可实现微电路 堆叠在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且凹坑覆盖可以 获得。
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9.发明申请Method of manufacturing package substrate with fine circuit pattern using anodic oxidation 失效使用阳极氧化制造具有精细电路图案的封装衬底的方法公开(公告)号：US20060046485A1
公开(公告)日：2006-03-02
申请号：US11011401
申请日：2004-12-13
申请人： Duck Maeng , Byung Sun , Tae Kim , Jee Mok , Jong Bae , Yoong Oh , Chang-Kyu Song , Suk-Hyeon Cho
发明人： Duck Maeng , Byung Sun , Tae Kim , Jee Mok , Jong Bae , Yoong Oh , Chang-Kyu Song , Suk-Hyeon Cho
IPC分类号： H01L21/302
CPC分类号： H01L21/486 , H01L23/142 , H01L2924/0002 , H05K3/205 , H05K3/207 , H05K3/4614 , H05K3/4617 , H05K3/4647 , H05K2203/0152 , H05K2203/0315 , H01L2924/00
摘要： Disclosed herein is a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. By anodizing a metal core which is opened through a masking process, oxidation layers are formed in open areas of the metal core to insulate portions of circuit pattern from each other. Further, by electroplating portions provided between the oxidation layers with copper or filling conductive paste between the oxidation layers using a screen, a package substrate having a fine circuit pattern is achieved.
摘要翻译： 本文公开了使用阳极氧化制造具有精细电路图案的封装衬底的方法。 通过对通过掩模工艺开放的金属芯进行阳极氧化，在金属芯的开放区域中形成氧化层，以使电路图案的部分彼此绝缘。 此外，通过使用屏幕将设置在氧化层之间的电镀部分用铜或在氧化层之间填充导电浆料，实现了具有精细电路图案的封装衬底。
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公开(公告)号：US20120103662A1
公开(公告)日：2012-05-03
申请号：US13064331
申请日：2011-03-18
申请人： Chang Bo Lee , Cheol Ho Choi , Yoong Oh
发明人： Chang Bo Lee , Cheol Ho Choi , Yoong Oh
CPC分类号： H05K3/3452 , H05K3/3436 , H05K2203/0278 , H05K2203/1476 , Y10T29/49155 , Y10T156/10
摘要： Disclosed herein are a printed circuit board including a first low-viscosity solder resist layer formed on one surface of a substrate having circuit patterns formed thereon and a second high-viscosity solder resist layer stacked on the first solder resist layer, thereby being advantageous in controlling the deviation in application thickness of solder resist (SR), while having excellent adhesion to the substrate, and a manufacturing method thereof.
摘要翻译： 这里公开了一种印刷电路板，其包括形成在其上形成有电路图案的基板的一个表面上的第一低粘度阻焊层和堆叠在第一阻焊层上的第二高粘度阻焊层，由此有利于控制 阻焊剂（SR）的应用厚度的偏差，同时对基板具有优异的粘附性及其制造方法。
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