Charge transfer memory and fabrication method thereof
    1.
    发明授权
    Charge transfer memory and fabrication method thereof 失效
    电荷转移记忆及其制造方法

    公开(公告)号:US4878103A

    公开(公告)日:1989-10-31

    申请号:US297651

    申请日:1989-01-17

    CPC分类号: G11C27/04 G11C19/287

    摘要: A charge transfer memory and its fabrication method are disclosed. The memory has charge transfer shift registers, with four phases and two level of electrodes, and a reading register with two phases and three levels of electrodes. At one end of each shift register, there is a final electrode contiguous with a reading storage electrode of the reading register, which is itself contiguous to a reading transfer electrode. These electrodes are made in a layer, with a second type of doping, of a semiconductor substrate with a first type of doping. Zones with a third type of doping are made facing the transfer electrodes of the reading register. According to the invention, facing the final electrode of each shift register, a zone with a fourth type of doping is made. This zone with a fourth type of doping prevents charges flowing in the reading register from returning to a shift register.

    摘要翻译: 公开了电荷转移存储器及其制造方法。 存储器具有电荷转移移位寄存器,具有四相和两电平电极,以及具有两相和三电平电平的读取寄存器。 在每个移位寄存器的一端,存在与读取寄存器的读取存储电极相邻的最终电极,其本身与读取转移电极相邻。 这些电极制成具有第一类掺杂的半导体衬底的具有第二类掺杂的层。 具有第三类掺杂的区域面向读取寄存器的转移电极。 根据本发明,面对每个移位寄存器的最终电极,制成具有第四类掺杂的区域。 具有第四类掺杂的区域防止在读取寄存器中流动的电荷返回到移位寄存器。

    Charge-coupled device with lowering of transfer potential at output and
fabrication method thereof
    2.
    发明授权
    Charge-coupled device with lowering of transfer potential at output and fabrication method thereof 失效
    电荷耦合器件输出转移电位降低及其制造方法

    公开(公告)号:US4873562A

    公开(公告)日:1989-10-10

    申请号:US287887

    申请日:1988-12-21

    CPC分类号: H01L29/76841

    摘要: Disclosed are a charge-coupled device with lowering of output potential as well as a method for the fabrication of this device. In a known way, the device comprises, upstream on a semiconducting substrate with a first type of doping (P), a semiconducting layer with a second type of doping (N) and an insulating layer covering the former layer. Pairs of electrodes are formed on the insulating layer. Each pair has a transfer electrode and a storage electrode. Zones with a third type of doping N.sup.+) are made in the layer of a second type (N). A layer with a third type of doping (N.sup.-) is made downstream, in the layer with a second type of doping, and, downstream, there is formed at least one other pair of additional transfer and storage electrodes. A zone with a fourth type of doping (N.sup.--) is made beneath the additional transfer electrode in the layer with a third type of doping (N.sup.-). This pair of additional electrodes and the zone with a fourth type of doping make it possible to obtain the lowering of transfer potential at output.

    摘要翻译: 公开了具有降低输出电位的电荷耦合器件以及用于制造该器件的方法。 以已知的方式,器件包括在具有第一类型掺杂(P)的半导体衬底上的上游,具有第二类型掺杂(N)的半导体层和覆盖前一层的绝缘层。 在绝缘层上形成一对电极。 每一对具有转移电极和存储电极。 在第二类型(N)的层中制造具有第三类掺杂N +的区域)。 在具有第二种类型的掺杂的层中,具有第三类掺杂(N-)的层被制成下游,并且在下游形成至少另外一对额外的转移和存储电极。 在具有第三类掺杂(N)的层中,在附加转移电极的下方形成具有第四类掺杂(N-)的区域。 这对附加电极和具有第四类掺杂的区域使得可以获得输出时的转移电位的降低。

    CONNECTION PAD STRUCTURE FOR AN IMAGE SENSOR ON A THINNED SUBSTRATE
    4.
    发明申请
    CONNECTION PAD STRUCTURE FOR AN IMAGE SENSOR ON A THINNED SUBSTRATE 有权
    用于薄膜基板上的图像传感器的连接板结构

    公开(公告)号:US20100314776A1

    公开(公告)日:2010-12-16

    申请号:US12518030

    申请日:2007-12-11

    申请人: Pierre Blanchard

    发明人: Pierre Blanchard

    IPC分类号: H01L23/52 H01L21/70

    摘要: The invention relates to the fabrication of electronic circuits on a thinned semiconductor substrate. To produce a connection pad on the back side of the thinned substrate, the procedure is as follows: an integrated circuit is produced on an unthinned substrate, in which a portion of a polycrystalline silicon layer (18) dedicated for the connection of the pad is provided. The circuit is transferred onto a transfer substrate (30) and then its back side is thinned. A via is opened in the thinned semiconductor layer (12) in order to gain access to the polycrystalline silicon; aluminum (80) is deposited and this layer is etched so as to define a pad which is in contact with the internal interconnects of the integrated circuit by way of the polycrystalline silicon.

    摘要翻译: 本发明涉及在薄型半导体衬底上制造电子电路。 为了在减薄的基板的背面上产生连接焊盘,过程如下:在未固化的衬底上产生集成电路,其中专用于焊盘连接的多晶硅层(18)的一部分是 提供。 电路被转印到转印衬底(30)上,然后将其背面变薄。 在减薄的半导体层(12)中打开通孔,以便进入多晶硅; 沉积铝(80),并且蚀刻该层以限定通过多晶硅与集成电路的内部互连接触的焊盘。

    Integrated circuit with a very small-sized reading diode
    5.
    发明申请
    Integrated circuit with a very small-sized reading diode 审中-公开
    具有非常小尺寸读数二极管的集成电路

    公开(公告)号:US20070184653A1

    公开(公告)日:2007-08-09

    申请号:US10591178

    申请日:2005-02-21

    申请人: Pierre Blanchard

    发明人: Pierre Blanchard

    IPC分类号: H01L21/44

    CPC分类号: H01L29/76816

    摘要: The invention relates to integrated circuits comprising both conductive gates deposited above a semiconductor substrate and a diode is formed between two electrodes. In order to achieve a diode of very small dimensions, the following procedure is adopted: producing the electrodes (ELn, GRST, then thermally oxidizing the electrodes, then exposing the surface of the substrate between the electrodes, then the following operations: depositing doped polycrystalline silicon in order to form one pole (42) of the diode, the substrate forming the other pole, delimiting a desired silicon pattern covering the space left between the electrodes and also covering a region lying outside this space, depositing an insulating layer, locally etching an opening into this insulating layer above the polycrystalline silicon outside the space lying between the electrodes, in order to form an offset contact zone, depositing a metal layer and etching the metal layer.

    摘要翻译: 本发明涉及包括沉积在半导体衬底上方的导电栅极和二极管之间的二极管的集成电路。 为了实现尺寸非常小的二极管,采用以下步骤:产生电极(ELn,GRST,然后热氧化电极,然后在电极之间暴露衬底的表面),然后进行以下操作:沉积掺杂多晶 硅以便形成二极管的一极(42),所述衬底形成另一极,限定覆盖留在电极之间的空间的期望的硅图案,并且还覆盖位于该空间外部的区域,沉积绝缘层,局部蚀刻 在位于电极之间的空间之外的多晶硅上方的绝缘层的开口,以形成偏移接触区,沉积金属层和蚀刻金属层。

    Mobile microwave link using waveguides
    6.
    发明授权
    Mobile microwave link using waveguides 失效
    移动微波链路使用波形

    公开(公告)号:US5245301A

    公开(公告)日:1993-09-14

    申请号:US878860

    申请日:1992-05-05

    IPC分类号: H01P1/06

    CPC分类号: H01P1/067

    摘要: This microwave link connects a fixed set of electronic equipment to a mobile set of electronic equipment that can be shifted between two extreme positions, at least one of which is an operating position. The link is, for example, one between a radar transceiver and a radar antenna that can be retracted into a silo. It is constituted by a sequence of rigid rectangular waveguide elements hinged at their ends by means of hinges comprising at least one rotating connector formed by two rectangular-window flanges, fitted together and rotational movable with respect to each other. This rotational connector has two operational positions at 180.degree. with respect to each other where it can transmit microwave power and where the rectangular windows of its flanges coincide, and it assumes one of these operational positions when the movable electronic equipment is in the operating position.

    摘要翻译: 该微波链路将固定的一组电子设备连接到移动的电子设备组件,该电子设备可以在两个极限位置之间移动,其中至少一个是操作位置。 该链路例如是雷达收发器和可以缩回到筒仓中的雷达天线之间的链路。 它由一系列刚性的矩形波导元件组成,它们通过铰链铰接在其端部,该铰链包括至少一个由两个矩形窗口法兰形成的旋转连接件,该两个矩形窗口凸缘彼此装配在一起并且可相对于彼此移动。 该旋转连接器相对于彼此具有180度的两个操作位置,其中它可以传递微波功率,并且其凸缘的矩形窗口重合,并且当可移动电子设备处于操作位置时,该操作位置处于这些操作位置之一。

    Process for producing silicide or silicon gates for an integrated
circuit having elements of the gate-insulator-semiconductor type
    8.
    发明授权
    Process for producing silicide or silicon gates for an integrated circuit having elements of the gate-insulator-semiconductor type 失效
    用于制造具有栅极 - 绝缘体 - 半导体型元件的集成电路的硅化物或硅栅的工艺

    公开(公告)号:US4679301A

    公开(公告)日:1987-07-14

    申请号:US782140

    申请日:1985-09-30

    摘要: A process for forming closely spaced silicon or silicon-silicide gate electrodes for an integrated circuit involving the successive deposition over the semiconductive substrate of layers of silicon oxide, polycrystalline silicon, a metal, for example, tantalum which can be converted to a silicide, an oxide layer and a masking layer. Then the masking layer is patterned by photolithography and the exposed oxide layer etched in a fashion to undercut the overlying masking layer to leave an overhang. Then the exposed metal layer is removed, and the metal forming a silicide redeposited through the opening in the masking layer on the central portion of the exposed polycrystalline corresponding to the opening. The metal is then converted to a silicide and the polycrystalline silicon free of the silicide is removed.

    摘要翻译: 用于形成用于集成电路的紧密间隔的硅或硅硅化物栅电极的方法,该集成电路涉及在二氧化硅,多晶硅,金属例如可转化为硅化物的钽的半导体衬底上的连续沉积, 氧化物层和掩模层。 然后通过光刻对掩模层进行图案化,并以暴露的氧化层蚀刻以削弱叠加的掩蔽层以留下悬垂的方式。 然后去除暴露的金属层,并且形成硅化物的金属通过对应于开口的暴露的多晶硅的中心部分上的掩模层中的开口再沉积。 然后将金属转化为硅化物,并且除去不含硅化物的多晶硅。

    SOFTWARE TOOL FOR WRITING SOFTWARE FOR ONLINE QUALIFICATION MANAGEMENT
    9.
    发明申请
    SOFTWARE TOOL FOR WRITING SOFTWARE FOR ONLINE QUALIFICATION MANAGEMENT 审中-公开
    软件工具,用于撰写在线资质管理软件

    公开(公告)号:US20110047528A1

    公开(公告)日:2011-02-24

    申请号:US12446042

    申请日:2007-10-16

    IPC分类号: G06F9/44

    CPC分类号: G06F8/20 G06Q10/06

    摘要: An online qualification management system that can be used to perform qualification management, such as candidate assessment for recruiting or promoting purposes, job description simulations, and learning management. A computing entity can execute a software application to implement a qualification management project that interacts online with a candidate to perform an assessment procedure on the candidate. The qualification management project includes a set of modules intended to interact individually with the candidate being assessed. One of the modules of the set may be a test module for testing the candidate for one or more skills. Another one of the modules of the set may be a virtual simulation module and implement a virtual simulation, the virtual simulation having a scenario defined by a chain of events and including a plurality of graphical scenes. The virtual simulation can also involve one or more avatars and/or interactive graphical objects. An author can use an authoring tool to create the qualification management project.

    摘要翻译: 可用于执行资格管理的在线资格管理系统,如招聘或推广目的候选人评估,工作描述模拟和学习管理。 计算实体可以执行软件应用程序来实施与候选者在线交互以对候选者执行评估程序的资格管理项目。 资格管理项目包括一组旨在与被评估候选人单独交互的模块。 该组件的一个模块可以是用于测试候选人的一种或多种技能的测试模块。 该组的另一个模块可以是虚拟模拟模块并实现虚拟仿真,虚拟模拟具有由事件链定义并包括多个图形场景的场景。 虚拟模拟还可以涉及一个或多个化身和/或交互式图形对象。 作者可以使用创作工具创建资格管理项目。

    Filler concentrates for use in thermoplastic materials
    10.
    发明授权
    Filler concentrates for use in thermoplastic materials 有权
    填充浓缩物用于热塑性材料

    公开(公告)号:US06951900B2

    公开(公告)日:2005-10-04

    申请号:US10203782

    申请日:2001-02-14

    CPC分类号: C08J3/226 C08J2423/00

    摘要: The invention relates to the use of isotactic polypropylenes of very great fluidity for the preparation of concentrates of fillers which can be used in thermoplastics of the olefinic type such as polypropylene, polyethylene and as a general rule: the polymers used alone or in a mixture, based on ethylenic monomers containing 2 to 6 atoms of carbon polymerized alone or in a mixture. The invention also relates to the concentrates of fillers or master batches prepared from isotactic polypropylenes of very great fluidity. The invention finally relates to the loaded thermoplastic materials obtained with the addition of selected polypropylenes according to the invention, and the industrial products manufactured from, or containing, such thermoplastic materials.

    摘要翻译: 本发明涉及非常大流动性的全同立构聚丙烯用于制备可用于烯烃类热塑性塑料如聚丙烯,聚乙烯的填料浓缩物,并且一般规则是:单独使用或混合使用的聚合物, 基于单独或以混合物聚合的含有2-6个碳原子的烯烃单体。 本发明还涉及由具有非常大流动性的全同立构聚丙烯制备的填料或母料的浓缩物。 本发明最终涉及通过添加根据本发明的选择的聚丙烯获得的装载的热塑性材料,以及由这种热塑性材料制造或包含这些热塑性材料的工业产品。