摘要:
The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zinesulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition. The ionic compatibilizer is present in a range from about 0.1 to about 2.0 mol-% of said composition. The cobalt salt is present in a range from about 20 to about 500 ppm of said composition.
摘要:
The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zincsulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition. The ionic compatibilizer is present in a range from about 0.1 to about 2.0 mol-% of said composition. The cobalt salt is present in a range from about 20 to about 500 ppm of said composition.
摘要:
The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zincsulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition. The ionic compatibilizer is present in a range from about 0.1 to about 2.0 mol-% of said composition. The cobalt salt is present in a range from about 20 to about 500 ppm of said composition.
摘要:
A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.
摘要:
A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要:
A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.
摘要翻译:提供具有等于或小于3.6的介电常数的富碳碳氮化硼介电膜,其可用作各种电子器件中的组分。 富碳碳氮化硼电介质膜具有C x B y N z的化学式,其中x为35原子%以上,y为6原子%〜32原子%,z为8原子%〜33原子%。
摘要:
An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.
摘要:
A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要:
A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要:
Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.