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    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
    4.
    发明申请
    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS 有权
    用于薄盒ETSOI MOSFET的稳定隔离

    公开(公告)号：US20130264641A1

    公开(公告)日：2013-10-10

    申请号：US13442168

    申请日：2012-04-09

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

    摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

    LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI
    6.
    发明申请
    LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效

    公开(公告)号：US20130015512A1

    公开(公告)日：2013-01-17

    申请号：US13605260

    申请日：2012-09-06

    申请人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    发明人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

    摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

    LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI
    7.
    发明申请
    LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效
    ETSOI的低电阻源和漏电延伸

    公开(公告)号：US20130015509A1

    公开(公告)日：2013-01-17

    申请号：US13183666

    申请日：2011-07-15

    申请人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    发明人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

    摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

    摘要翻译： 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

    STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
    8.
    发明申请
    STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES 有权
    非平面半导体器件中应力锁定的结构和方法

    公开(公告)号：US20120018730A1

    公开(公告)日：2012-01-26

    申请号：US12841408

    申请日：2010-07-22

    申请人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L27/0886 ,  H01L21/82 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785

    摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.

    摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向晶体结构的重结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。

    Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species
    9.
    发明授权
    Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species 有权
    通过使用有机分子物种的气体簇的GCIB表面处理来修复工艺引起的介电损伤的方法

    公开(公告)号：US07838428B2

    公开(公告)日：2010-11-23

    申请号：US11609040

    申请日：2006-12-11

    申请人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

    发明人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

    IPC分类号： H01L21/311

    CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831

    摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

    摘要翻译： 当互连结构构建在多孔超低k（ULK）材料上时，沟槽和/或通孔的底部和/或侧壁通常被以下金属化或清洁工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供一种通过在层间电介质（ILD）材料上形成互连结构来修复工艺引起的介电损伤的方法。 该方法包括处理ILD材料的暴露区域以产生富含碳的区域，以及使富含碳的区域金属化。 一个实施例包括通过使用通过包括直链或支链，脂族或芳族烃的气体产生的气体簇离子束（GCIB）照射暴露区域来向ILD材料的暴露的侧壁区域提供处理以产生富碳区域 ，并且富含碳的区域金属化。

    METHOD TO MAKE SINGLE-LAYER PET BOTTLES WITH HIGH BARRIER AND IMPROVED CLARITY
    10.
    发明申请
    METHOD TO MAKE SINGLE-LAYER PET BOTTLES WITH HIGH BARRIER AND IMPROVED CLARITY 无效
    制备单层PET瓶的方法，具有高阻挡和改善的清晰度

    公开(公告)号：US20100209641A1

    公开(公告)日：2010-08-19

    申请号：US12768541

    申请日：2010-04-27

    申请人： Zhenguo LIU ,  Sanjay Mehta ,  Xiaoyan Huang ,  David A. Schiraldi

    发明人： Zhenguo LIU ,  Sanjay Mehta ,  Xiaoyan Huang ,  David A. Schiraldi

    IPC分类号： B32B1/02 ,  C08L77/00

    CPC分类号： C08K3/24 ,  B29B2911/1402 ,  B29B2911/14026 ,  B29B2911/14033 ,  B29B2911/1404 ,  B29B2911/14106 ,  B29B2911/14133 ,  B29B2911/1416 ,  B29C49/0005 ,  B29C49/06 ,  B29K2067/00 ,  B65D1/0207 ,  C08G63/6886 ,  C08K5/098 ,  C08K5/42 ,  C08L67/02 ,  C08L77/06 ,  Y10T428/13 ,  Y10T428/1352 ,  Y10T428/139 ,  C08L2666/20

    摘要： The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zinesulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition. The ionic compatibilizer is present in a range from about 0.1 to about 2.0 mol-% of said composition. The cobalt salt is present in a range from about 20 to about 500 ppm of said composition.

    摘要翻译： 本发明包括聚酯和部分芳族聚酰胺与离子增容剂和钴盐的共混物。 与现有技术中已知的容器相比，该混合物可以加工成具有主动和被动氧气阻隔性和二氧化碳阻隔性能的容器，其颜色和透明度得到改善。 部分芳族聚酰胺优选为间二甲苯基己二酰胺。 离子增容剂优选为5-钠磺基间苯二甲酸或5-锌磺基间苯二甲酸或其二烷基酯，如二甲酯（SIM）和乙二醇酯（SIPEG）。 钴盐选自乙酸钴，碳酸钴，氯化钴，氢氧化钴，环烷酸钴，油酸钴，亚油酸钴，辛酸钴，硬脂酸钴，硝酸钴，磷酸钴，硫酸钴，钴（乙醇酸）等。 ，或这些中的两种或更多种的混合物。 部分芳族聚酰胺的存在量为约1至约10重量％。 ％的所述组合物。 离子相容剂的存在量为所述组合物的约0.1至约2.0mol％。 钴盐以所述组合物的约20至约500ppm的范围存在。