公开(公告)号：US20240347585A1

公开(公告)日：2024-10-17

申请号：US18753743

申请日：2024-06-25

申请人： MaxPower Semiconductor, Inc.

发明人： Jun Zeng ,  Mohamed Darwish ,  Shih-Tzung Su

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813

摘要： A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions may be formed in trench areas that are deeper than the active gate trench areas.

公开(公告)号：US20240339494A1

公开(公告)日：2024-10-10

申请号：US18625100

申请日：2024-04-02

申请人： MaxPower Semiconductor, Inc.

发明人： Mohamed Darwish ,  Jun Zeng

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0611 ,  H01L29/7813 ,  H01L29/7832

摘要： A vertical MOSFET has an N-type drift layer over an N+ substrate. A horizontal JFET layer overlies the drift layer, where the JFET layer has P-type gate regions and N-type channel regions. A first N-type layer overlies the JFET layer. A P-type well layer overlies the first N-type layer. Gate trenches are formed through the P-type well layer and into the first N-type layer. N-type source regions abut the top areas of the gate trenches, and a source electrode contacts the source regions. The JFET N-type channel regions are generally directly below the gate trenches for conducting a vertical current when the MOSFET is in an on state. The source electrode is electrically connected to the JFET P-type gate regions via a deep P-type contact region. The JFET N-type channel regions pinch off during short circuit high current conditions to limit drain current.

公开(公告)号：US11316021B2

公开(公告)日：2022-04-26

申请号：US16991935

申请日：2020-08-12

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06

摘要： A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.

公开(公告)号：US20180337230A1

公开(公告)日：2018-11-22

申请号：US16014635

申请日：2018-06-21

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC分类号： H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L29/0611 ,  H01L21/26586 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8611

摘要： Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

公开(公告)号：US10128353B2

公开(公告)日：2018-11-13

申请号：US15809863

申请日：2017-11-10

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/36 ,  H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

摘要： Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US09385227B2

公开(公告)日：2016-07-05

申请号：US14027873

申请日：2013-09-16

申请人： MaxPower Semiconductor, Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

摘要： Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

公开(公告)号：US20160064497A1

公开(公告)日：2016-03-03

申请号：US14840744

申请日：2015-08-31

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/40 ,  H03K17/687 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

摘要： N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

摘要翻译： 其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。 除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。

公开(公告)号：US09093522B1

公开(公告)日：2015-07-28

申请号：US14338303

申请日：2014-07-22

申请人： MaxPower Semiconductor, Inc.

发明人： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811

摘要： A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

摘要翻译： 功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长低掺杂浓度的N型漂移层。 在漂移层上形成交替的N型和P型列，掺杂浓度较高。 然后形成具有比漂移区更高的掺杂剂浓度的N型层并蚀刻以具有侧壁。 在N型层中形成P阱，在P阱中形成N +源极区。 在P阱的横向通道上形成一个栅极，并且在侧壁上形成一个垂直场板。 源电极接触P阱和源极区。 正栅极电压反转横向沟道并增加沿着侧壁的导电。 源极和漏极之间的电流横向流动，然后垂直穿过各种N层。 导通电阻降低，击穿电压增加。

公开(公告)号：US20150076593A1

公开(公告)日：2015-03-19

申请号：US14027873

申请日：2013-09-16

申请人： MaxPower Semiconductor, Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

摘要： Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

摘要翻译： 侧向功率器件，其中静电静电电荷放置在与漂移区相邻的电介质材料中。 屏蔽栅极介于栅电极和漏极之间，以减少米勒电荷。 在一些实施例中，栅电极是沟槽栅极，并且在这种情况下，屏蔽电极也优选地垂直延伸。

公开(公告)号：US08946769B2

公开(公告)日：2015-02-03

申请号：US14168300

申请日：2014-01-30

申请人： MaxPower Semiconductor, Inc.

发明人： Mohamed N. Darwish ,  Amit Paul

IPC分类号： H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L21/263 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/408 ,  H01L21/263 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838

摘要： A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.