公开(公告)号：US20240282841A1

公开(公告)日：2024-08-22

申请号：US18139945

申请日：2023-04-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Po-Hsien Yeh ,  Jih-Wen Chou ,  Hwi-Huang Chen ,  Hsin-Hong Chen ,  Yu-Jen Huang

IPC分类号： H01L29/66 ,  H01L21/223 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/2233 ,  H01L21/2236 ,  H01L29/7786 ,  H01L21/022 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192

摘要： A GaN device with N2 pre-treatment is provided in the present invention, including a GaN substrate, an AlGaN layer covering the GaN substrate, a p-GaN gate on the AlGaN layer, a TiN electrode on the p-GaN gate, a first dielectric layer on the AlGaN layer surrounding the p-GaN gate, wherein a horizontal spacing is between the first dielectric layer and the p-GaN gate, and an interface between the AlGaN layer and the GaN substrate not covered by the first dielectric layer is subject to N2 pre-treatment, and a second dielectric layer covering on and directly contacting the exposed first dielectric layer, AlGaN layer, p-GaN gate and TiN electrode.

公开(公告)号：US20240274673A1

公开(公告)日：2024-08-15

申请号：US18300372

申请日：2023-04-13

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Robin Christine Hwang ,  Jih-Wen Chou ,  Hwi-Huang Chen ,  Hsin-Hong Chen ,  Yu-Jen Huang ,  Chih-Hung Lu

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/404 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

摘要： A HEMT device including a substrate structure, a channel layer, a barrier layer, a gate electrode, a drain electrode, a first source field plate, a second source field plate, and a dielectric structure is provided. The first source field plate extends from the second side of the gate electrode to the first side of the gate electrode. The second source field plate is located on the first side of the gate electrode and is located between the drain electrode and the first source field plate. There is a gap between the first source field plate and the second source field plate. The first source field plate has an end adjacent to the gap. The thickness of the dielectric structure located directly below the second source field plate is greater than the thickness of the dielectric structure located directly below the end of the first source field plate.

公开(公告)号：US12040343B2

公开(公告)日：2024-07-16

申请号：US17458586

申请日：2021-08-27

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Jun-Ming Su ,  Chih-Ping Chung ,  Ming-Yu Ho

IPC分类号： H01L27/00 ,  H01L27/146

CPC分类号： H01L27/1464 ,  H01L27/1461 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14689

摘要： A backside illuminated image sensor, including a semiconductor layer, a first gate structure, and a light sensing device, is provided. The semiconductor layer has a first surface and a second surface opposite to each other. The first gate structure is disposed on the second surface. The light sensing device is located in the semiconductor layer. The light sensing device extends from the first surface to the second surface.

公开(公告)号：US20240162082A1

公开(公告)日：2024-05-16

申请号：US18150795

申请日：2023-01-06

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Ya-Ting Chen ,  Pin-Chieh Huang

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/481 ,  H01L24/80 ,  H01L21/76877 ,  H01L2224/80896

摘要： A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.

公开(公告)号：US11984158B2

公开(公告)日：2024-05-14

申请号：US17747998

申请日：2022-05-18

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Zih-Song Wang

IPC分类号： G11C13/00 ,  G11C5/06 ,  H03K19/017

CPC分类号： G11C13/0028 ,  G11C5/063 ,  G11C13/0026 ,  G11C13/0038 ,  H03K19/01742

摘要： An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.

公开(公告)号：US20240145244A1

公开(公告)日：2024-05-02

申请号：US18155723

申请日：2023-01-17

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Yun-An Chen ,  Hsiao-Shan Huang ,  Hsiao-Chiang Lin

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76816

摘要： A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.

公开(公告)号：US20240131655A1

公开(公告)日：2024-04-25

申请号：US17994411

申请日：2022-11-28

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Ming-Hsiang Chen ,  Shih-Ci Yen ,  Kai-Yao Shih

IPC分类号： B24B37/32 ,  B24B37/04

CPC分类号： B24B37/32 ,  B24B37/042

摘要： The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.

公开(公告)号：US20240079485A1

公开(公告)日：2024-03-07

申请号：US17975559

申请日：2022-10-27

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Jih-Wen Chou ,  Chih-Hung Lu ,  Bo-An Tsai ,  Zheng-Chang Mu ,  Po-Hsien Yeh ,  Robin Christine Hwang

IPC分类号： H01L29/778 ,  H01L21/768 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/76843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/6656

摘要： A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

公开(公告)号：US20240071901A1

公开(公告)日：2024-02-29

申请号：US17950057

申请日：2022-09-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wei-Yu Lin

IPC分类号： H01L23/522 ,  H01G4/232 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01G4/232 ,  H01L28/75

摘要： A capacitor structure including a substrate, an insulating layer, a capacitor, a shielding layer, a first connection terminal, and a second connection terminal is disposed. The insulating layer is disposed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, a dielectric layer. The first electrode layer is disposed on the insulating layer. The second electrode layer is disposed on the first electrode layer. The dielectric layer is disposed between the first electrode layer and the second electrode layer. The shielding layer is disposed in the insulating layer. The shielding layer is located between the first electrode layer and the substrate. The first connection terminal is electrically connected to the first electrode layer. The second connection terminal is electrically connected to the second electrode layer.

公开(公告)号：US11915969B2

公开(公告)日：2024-02-27

申请号：US17687663

申请日：2022-03-06

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chen-Chiang Liu ,  Hung-Kwei Liao

IPC分类号： H01L21/762 ,  H01L23/373 ,  H01L27/082 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/76224 ,  H01L23/3736 ,  H01L21/763 ,  H01L27/082 ,  H01L27/1203

摘要： A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.