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    Gain control in complementary common gate and common source amplifiers
    3.
    发明授权
    Gain control in complementary common gate and common source amplifiers 有权
    互补公共门和公共源放大器的增益控制

    公开(公告)号：US09407226B2

    公开(公告)日：2016-08-02

    申请号：US14575851

    申请日：2014-12-18

    申请人： QUALCOMM Incorporated

    发明人： Chih-Fan Liao

    IPC分类号： H03F1/22 ,  H03G3/30 ,  H03F3/19

    CPC分类号： H03G3/3036 ,  H03F1/0272 ,  H03F1/0277 ,  H03F3/19 ,  H03F3/193 ,  H03F3/265 ,  H03F3/45654 ,  H03F2200/451 ,  H03F2200/54 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/45228 ,  H03F2203/45731 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/3052

    摘要： Gain control in complementary common gate and common source amplifiers is disclosed. In an exemplary embodiment, an apparatus includes a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal. The first amplifier stage includes a current diverter that selectively diverts current to set a gain of the first amplifier stage. The apparatus also includes a second amplifier stage configured to amplify the input signal at the input terminal to generate a second amplified signal. The second amplifier stage includes a gain control circuit to set a gain of the second amplifier stage.

    摘要翻译： 公开了互补公共栅极和公共源放大器中的增益控制。 在示例性实施例中，一种装置包括：第一放大器级，被配置为放大输入端的输入信号以产生第一放大信号。 第一放大器级包括电流分流器，其选择性地转移电流以设置第一放大器级的增益。 该装置还包括第二放大器级，被配置为放大输入端的输入信号以产生第二放大信号。 第二放大级包括用于设定第二放大级的增益的增益控制电路。

    Amplifier
    4.
    发明授权
    Amplifier 有权
    放大器

    公开(公告)号：US09300253B2

    公开(公告)日：2016-03-29

    申请号：US14530028

    申请日：2014-10-31

    申请人： FUJITSU SEMICONDUCTOR LIMITED

    发明人： Nobumasa Hasegawa

    IPC分类号： H03F1/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/24 ,  H03F3/45

    CPC分类号： H03F1/0266 ,  H03F1/3211 ,  H03F3/245 ,  H03F3/45475 ,  H03F2200/411 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/555 ,  H03F2203/45051 ,  H03F2203/45112 ,  H03F2203/45228 ,  H03F2203/45244

    摘要： An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.

    摘要翻译： 放大器包括被配置为输出第一差分信号的第一变压器，耦合到第一变压器的第一差分放大器，耦合到第一差分放大器的第二变压器，耦合到第二变压器的第二差分放大器，被配置为转换第二变换器 差分信号从第二差分放大器输出到单端输出信号，以及第一偏置电路，其被配置为向第一变压器的第一次级线圈提供第一偏置电压，其中第一偏置电路将第一偏置电压设置为 基于在输出信号的功率大于或等于第一功率的第一操作区域中的输入信号的电压大于或等于第一电压，使得输出信号的功率增益特性变得更接近于其中增益 的输出信号变为恒定。

    HF mixing stage in the form of a common-base circuit
    5.
    发明授权
    HF mixing stage in the form of a common-base circuit 失效
    HF混合阶段形式为共基电路

    公开(公告)号：US5584069A

    公开(公告)日：1996-12-10

    申请号：US255915

    申请日：1994-06-07

    申请人： Hans Sapotta ,  Heinz Rinderle

    发明人： Hans Sapotta ,  Heinz Rinderle

    IPC分类号： H03D7/14 ,  H04B1/28

    CPC分类号： H03D7/1425 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0019 ,  H03D2200/0033 ,  H03D2200/0088 ,  H03F2203/45198 ,  H03F2203/45208 ,  H03F2203/45228 ,  H03F2203/45458 ,  H03F2203/45464

    摘要： HF mixing stage in the form of a common-base circuit including: two bipolar amplifying transistors; two switching stages each assigned to an amplifying transistor and each having two emitter-coupled bipolar switching transistors and with two signal sources which supply the bases of the switching transistors with superimposed signals; two nodes at which the emitters of the switching transistors are connected to the collector of the associated amplifying transistor; two further output nodes at which the collectors of each of two switching transistors in different switching stages are connected together; circuit elements for electrical isolation through which the emitters of the amplifying transistors are connected together; an input signal source with associated internal resistor of which the one terminal is connected via the circuit input to the circuit elements for electrical isolation and the other terminal is connected to reference potential and whose signal is to be transposed into another frequency range through the mixing stage; and wherein: the two bipolar amplifying transistors are of different conduction type, and the two switching transistors of a respective switching stage are of the same conduction type as the associated bipolar amplifying transistor.

    摘要翻译： HF混频阶段形式为公共基极电路，包括：双极放大晶体管; 两个开关级各自分配给放大晶体管，每个开关级具有两个发射极耦合双极开关晶体管，并具有两个信号源，它们以叠加的信号提供开关晶体管的基极; 开关晶体管的发射极连接到相关放大晶体管的集电极的两个节点; 两个另外的输出节点，不同开关级的两个开关晶体管中的每一个的集电极连接在一起; 用于电隔离的电路元件，放大晶体管的发射极通过该元件连接在一起; 具有相关联的内部电阻器的输入信号源，其一个端子经由电路输入连接到电路元件用于电隔离，另一个端子连接到参考电位，并且其信号将通过混频阶段被转置到另一个频率范围 ; 并且其中：所述两个双极放大晶体管具有不同的导通类型，并且各个开关级的两个开关晶体管具有与相关联的双极放大晶体管相同的导通类型。

    GROUND FAULT CIRCUIT INTERRUPTER AND METHOD
    7.
    发明申请
    GROUND FAULT CIRCUIT INTERRUPTER AND METHOD 有权
    接地故障电路中断器和方法

    公开(公告)号：US20160233837A1

    公开(公告)日：2016-08-11

    申请号：US15132775

    申请日：2016-04-19

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Riley D. Beck ,  Scott R. Grange

    IPC分类号： H03F1/30 ,  G01R27/18 ,  H02H3/33 ,  G01R31/02 ,  H03F3/45 ,  H02H3/16

    CPC分类号： H03F1/303 ,  G01R27/18 ,  G01R31/025 ,  H02H1/0092 ,  H02H1/04 ,  H02H3/162 ,  H02H3/33 ,  H03F3/45 ,  H03F2203/45152 ,  H03F2203/45228 ,  H03F2203/45288

    摘要： A method and circuit for dynamically correcting offsets associated with an AC power system. In an embodiment, a first offset current generated in response to a ground to neutral fault stimulus is decreased and a second offset current generated in response to a differential fault stimulus is decreased. In another embodiment, the circuit includes an offset correction circuit that has one of a chopper circuit or an auto-zeroing circuit. An amplifier is connected to the offset correction circuit and an output connected to the offset correction circuit. A signal generator is switchably coupled to a first input of the offset correction circuit and a bias generator is switchably coupled to the first input of the offset correction circuit.

    摘要翻译： 一种用于动态校正与交流电力系统相关联的偏移的方法和电路。 在一个实施例中，响应于接地到中性故障刺激而产生的第一偏移电流减小，并且响应于差分故障刺激而产生的第二偏移电流减小。 在另一个实施例中，电路包括具有斩波电路或自动归零电路之一的偏移校正电路。 放大器连接到偏移校正电路和连接到偏移校正电路的输出。 信号发生器可切换地耦合到偏移校正电路的第一输入端，并且偏置发生器可切换地耦合到偏移校正电路的第一输入端。

    AMPLIFIER
    8.
    发明申请
    AMPLIFIER 有权
    放大器

    公开(公告)号：US20150130540A1

    公开(公告)日：2015-05-14

    申请号：US14530028

    申请日：2014-10-31

    申请人： FUJITSU SEMICONDUCTOR LIMITED

    发明人： Nobumasa HASEGAWA

    IPC分类号： H03F3/45 ,  H03F1/02

    CPC分类号： H03F1/0266 ,  H03F1/3211 ,  H03F3/245 ,  H03F3/45475 ,  H03F2200/411 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/555 ,  H03F2203/45051 ,  H03F2203/45112 ,  H03F2203/45228 ,  H03F2203/45244

    摘要： An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.

    摘要翻译： 放大器包括被配置为输出第一差分信号的第一变压器，耦合到第一变压器的第一差分放大器，耦合到第一差分放大器的第二变压器，耦合到第二变压器的第二差分放大器，被配置为转换第二变换器 差分信号从第二差分放大器输出到单端输出信号，以及第一偏置电路，其被配置为向第一变压器的第一次级线圈提供第一偏置电压，其中第一偏置电路将第一偏置电压设置为 基于在输出信号的功率大于或等于第一功率的第一操作区域中的输入信号的电压大于或等于第一电压，使得输出信号的功率增益特性变得更接近于其中增益 的输出信号变为恒定。

    Low cost monolithic gallium arsenide upconverter chip
    9.
    发明授权
    Low cost monolithic gallium arsenide upconverter chip 失效
    低成本单片砷化镓上变频芯片

    公开(公告)号：US5625307A

    公开(公告)日：1997-04-29

    申请号：US845293

    申请日：1992-03-03

    申请人： Norman R. Scheinberg

    发明人： Norman R. Scheinberg

    IPC分类号： H03D7/12 ,  H03D7/14 ,  H03D7/18 ,  H03D9/06 ,  H03B19/00 ,  H01L25/00 ,  H04B1/28

    CPC分类号： H03F3/45197 ,  H03D7/125 ,  H03D7/14 ,  H03D7/1408 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/1491 ,  H03D9/0675 ,  H01L2924/0002 ,  H03D2200/0019 ,  H03D2200/0025 ,  H03D2200/0027 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03D7/18 ,  H03F2203/45228 ,  H03F2203/45256 ,  H03F2203/45258 ,  H03F2203/45458 ,  H03F2203/45464 ,  H03F2203/45466

    摘要： A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

    摘要翻译： 描述了执行双转换有线电视（CATV）接收机的第一次频率转换的单片上变频器集成电路。 上变频器芯片包括三个功能块：吉尔伯特型图像抑制混频器，分相器和压控振荡器。 混合是通过一种新颖的吉尔伯特式混合器进行，包括镜像抑制电感器，以改善混频器的噪声系数。 差分电路拓扑结构允许单片上变频器芯片利用塑料双列直插蝙蝠包装，而不会造成相当大的性能损失。 以串联RC端接形式的片上RF旁路网络还有助于补偿双列直插封装中引脚电感的不良影响。 基于电阻器的直流偏置方案可大大降低上电延迟，从而实现更快的测试。

    Low cost monolithic GaAs upconverter chip
    10.
    发明授权
    Low cost monolithic GaAs upconverter chip 失效
    低成本单片GaAs上变频芯片

    公开(公告)号：US5563545A

    公开(公告)日：1996-10-08

    申请号：US312730

    申请日：1994-09-27

    申请人： Norman R. Scheinberg

    发明人： Norman R. Scheinberg

    IPC分类号： H03D7/12 ,  H03D7/14 ,  H03D7/18 ,  H03D9/06 ,  H03K17/16 ,  H03K17/687

    CPC分类号： H03F3/45197 ,  H03D7/125 ,  H03D7/14 ,  H03D7/1408 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/1491 ,  H03D9/0675 ,  H01L2924/0002 ,  H03D2200/0019 ,  H03D2200/0025 ,  H03D2200/0027 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03D7/18 ,  H03F2203/45228 ,  H03F2203/45256 ,  H03F2203/45258 ,  H03F2203/45458 ,  H03F2203/45464 ,  H03F2203/45466

    摘要： A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

    摘要翻译： 描述了执行双转换有线电视（CATV）接收机的第一次频率转换的单片上变频器集成电路。 上变频器芯片包括三个功能块：吉尔伯特型图像抑制混频器，分相器和压控振荡器。 混合是通过一种新颖的吉尔伯特式混合器进行，包括镜像抑制电感器，以改善混频器的噪声系数。 差分电路拓扑结构允许单片上变频器芯片利用塑料双列直插蝙蝠包装，而不会造成相当大的性能损失。 以串联RC端接形式的片上RF旁路网络还有助于补偿双列直插封装中引脚电感的不良影响。 基于电阻器的直流偏置方案可大大降低上电延迟，从而实现更快的测试。