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    Process of producing heterojunction bipolar transistor with silicon-germanium base
    2.
    发明授权
    Process of producing heterojunction bipolar transistor with silicon-germanium base 失效
    用硅锗基制造异质结双极晶体管的工艺

    公开(公告)号：US5494836A

    公开(公告)日：1996-02-27

    申请号：US460259

    申请日：1995-06-02

    申请人： Kiyotaka Imai

    发明人： Kiyotaka Imai

    IPC分类号： H01L29/165 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

    CPC分类号： H01L29/66242 ,  H01L29/7378 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/068 ,  Y10S148/069 ,  Y10S148/072 ,  Y10S438/969

    摘要： The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

    摘要翻译： 本发明提供了一种具有低反射性SiGe基极的异质结双极晶体管，即使在液氮温度附近的低温下电流增益和截止频率也较高。 晶体管制造工艺包括在硅衬底上形成n型集电极层和在集电极层上形成电介质膜，在电介质膜上形成具有开口的p +型多晶硅的基极，各向同性地蚀刻集电极上的电介质膜 通过使用基极的开口形成窗口，在由窗户露出的集电极层上形成p +型硅的外部基底层，选择性地蚀刻外部基底层以在中心区域形成孔，形成 p型SiGe本征基层，然后在本征基极层上形成n +型发射极。

    Heterojunction bipolar transistor with silicon-germanium base
    5.
    发明授权
    Heterojunction bipolar transistor with silicon-germanium base 失效
    异质结双极晶体管与硅锗基

    公开(公告)号：US5506427A

    公开(公告)日：1996-04-09

    申请号：US223500

    申请日：1994-04-05

    申请人： Kiyotaka Imai

    发明人： Kiyotaka Imai

    IPC分类号： H01L29/165 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328 ,  H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/7378 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/068 ,  Y10S148/069 ,  Y10S148/072 ,  Y10S438/969

    摘要： The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

    摘要翻译： 本发明提供了一种具有低反射性SiGe基极的异质结双极晶体管，即使在液氮温度附近的低温下电流增益和截止频率也较高。 晶体管制造工艺包括在硅衬底上形成n型集电极层和在集电极层上形成电介质膜，在电介质膜上形成具有开口的p +型多晶硅的基极，各向同性地蚀刻集电极上的电介质膜 通过使用基极的开口形成窗口，在由窗户露出的集电极层上形成p +型硅的外部基底层，选择性地蚀刻外部基底层以在中心区域形成孔，形成 p型SiGe本征基层，然后在本征基极层上形成n +型发射极。

    Method of fabricating multilayer circuits
    7.
    发明授权
    Method of fabricating multilayer circuits 失效
    制造多层电路的方法

    公开(公告)号：US3770529A

    公开(公告)日：1973-11-06

    申请号：US3770529D

    申请日：1970-08-25

    申请人： IBM

    发明人： ANDERSON L

    IPC分类号： H01L21/48 ,  H05K3/10 ,  B23K27/00

    CPC分类号： H05K3/101 ,  H01L21/486 ,  Y10S148/069 ,  Y10T29/49163 ,  Y10T29/49165

    摘要： Multiple level ceramic circuit structures are formed after the individual ceramic ''''green'''' sheets are machined using beams of radiation. Vias and channels are formed simultaneously in the individual ''''green'''' sheets by exposure of the sheet through a mask having apertures with predetermined dimensions. The method of fabricating the vias and channels recognizes the relationship between the size of the mask aperture and the depth of the machining in the ''''green'''' sheet by the beam of radiation. After stacking, registering and laminating the ''''green'''' sheets, they are sintered to a unitized state and only then metallized.

    摘要翻译： 在使用辐射束加工单个陶瓷“绿色”片材之后形成多层陶瓷电路结构。 通过使片材通过具有预定尺寸的孔的面罩曝光，在各个“绿色”片材中同时形成通道和通道。 制造通孔和通道的方法识别出通过辐射束在“绿色”片材中掩模孔径的尺寸和加工深度之间的关系。 在堆叠，登记和层压“绿色”片材之后，将它们烧结成单一化状态，然后仅金属化。