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公开(公告)号：US12096147B2
公开(公告)日：2024-09-17
申请号：US17878285
申请日：2022-08-01
发明人： Sung Yong Kim , Kyung-Min Kim , Hyuk Oh , Hyeok Jong Lee , Seung Hoon Jung , Woong Joo , Hee Sung Chae
IPC分类号： H04N25/75 , H04N25/709 , H03M1/56
CPC分类号： H04N25/75 , H04N25/709 , H03M1/56
摘要： An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
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公开(公告)号：US11870455B2
公开(公告)日：2024-01-09
申请号：US18080144
申请日：2022-12-13
发明人： Zhisheng Li , Jia Guo
CPC分类号： H03M1/34 , G06F1/04 , G06F7/501 , H03M1/14 , G06F1/0321 , H03M1/56 , H04N25/75 , H04N25/772
摘要： An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.
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公开(公告)号：US20230328407A1
公开(公告)日：2023-10-12
申请号：US17715780
申请日：2022-04-07
发明人： Trung Thanh Nguyen
IPC分类号： H04N5/3745 , H03M1/12 , H03M1/34 , H03M1/56
CPC分类号： H04N5/37455 , H03M1/1265 , H03M1/34 , H03M1/56 , H04N5/37457 , H04N5/378
摘要： A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.
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公开(公告)号：US11696053B2
公开(公告)日：2023-07-04
申请号：US17948908
申请日：2022-09-20
发明人： Atsumi Niwa , Yosuke Ueno , Shimon Teshima , Daijiro Anai , Yoshinobu Furusawa , Taishin Yoshida , Takahiro Uchimura , Eiji Hirata
IPC分类号： H04N25/75 , H04N25/70 , H04N25/13 , H04N25/772 , H04N25/778 , H01L27/146 , H03M1/12 , H03M1/56
CPC分类号： H04N25/75 , H01L27/14612 , H01L27/14621 , H01L27/14636 , H01L27/14645 , H04N25/134 , H04N25/70 , H04N25/772 , H04N25/778 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N2209/045
摘要： There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
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公开(公告)号：US11659302B1
公开(公告)日：2023-05-23
申请号：US17540434
申请日：2021-12-02
发明人： Chao-Fang Tsai , Zheng Yang , Chun-Hsiang Chang
IPC分类号： H04N25/772 , H03M1/46 , H03M1/56 , H04N25/75 , H03M1/12
CPC分类号： H04N25/772 , H03M1/462 , H03M1/468 , H03M1/56 , H04N25/75
摘要： A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
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公开(公告)号：US11627269B2
公开(公告)日：2023-04-11
申请号：US17516010
申请日：2021-11-01
摘要： An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.
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公开(公告)号：US11595030B2
公开(公告)日：2023-02-28
申请号：US16867399
申请日：2020-05-05
发明人： Lihang Fan , Liang Zuo , Nijun Jiang , Min Qu , Xuelian Liu
摘要： A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.
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8.发明授权公开(公告)号：US11531728B2
公开(公告)日：2022-12-20
申请号：US16805764
申请日：2020-02-29
申请人： TETRAMEM INC.
发明人： Ning Ge
摘要： Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.
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公开(公告)号：US11528440B2
公开(公告)日：2022-12-13
申请号：US17497558
申请日：2021-10-08
发明人： Sung Yong Kim , Myung Lae Chu , Min Woong Seo , Jun An Lee
IPC分类号： H04N5/376 , H04N5/374 , H04N5/369 , H04N5/378 , H03M1/56 , H03M1/82 , H04N5/3745 , H04N5/365
摘要： A digital pixel sensor for correcting and reducing a mismatch between a pixel and an analog digital converter provided. The digital pixel sensor includes a pixel array including a plurality of pixels; and a bank disposed on the pixel array. The bank includes: a plurality of comparators disposed on the plurality of pixels and configured to compare each of a plurality of pixel signals output from the plurality of pixels with a reference signal to output a plurality of comparison result signals; and a counter connected to the plurality of comparators, and configured to receive the plurality of comparison result signals and latch count code based on the plurality of comparison result signals.
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公开(公告)号：US11490043B2
公开(公告)日：2022-11-01
申请号：US17088692
申请日：2020-11-04
发明人： Yusuke Tokunaga
IPC分类号： H04N5/378 , H04N5/243 , H01L27/146 , H03M1/56
摘要： An imaging device includes a pixel array, a first converter, a second converter, a first ramp signal generation circuit that is disposed closer to the first converter than to the second converter and supplies a first ramp signal to the first converter and the second converter, a first connection line having one end connected to an output terminal of the first ramp signal generation circuit and including a portion extending away from an input terminal of the first converter in a path from the one end to the other end of the first connection line, and a second connection line having one end connected to the other end of the first connection line and the other end connected to the input terminal and including a portion extending closer to the input terminal in a path from the one end to the other end of the second connection line.
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