公开(公告)号：WO2006130558A3

公开(公告)日：2009-04-16

申请号：PCT/US2006020749

申请日：2006-05-31

Applicant: UNIV ILLINOIS ,  LIU CHANG ,  CHEN NANNAN

Inventor： LIU CHANG ,  CHEN NANNAN

IPC: B81B5/00 ,  B81C3/00 ,  B82B1/00 ,  B82B3/00 ,  H01L21/302

CPC classification number: H05K1/0289 ,  B81C99/008 ,  D03D1/0088 ,  D03D9/00 ,  D03D15/00 ,  D03D15/0066 ,  D10B2101/06 ,  D10B2101/08 ,  D10B2101/20 ,  D10B2401/16 ,  D10B2401/20 ,  D10B2403/02431 ,  H01L51/0021 ,  H01L51/0097 ,  H01L51/5203 ,  H05K1/038 ,  H05K3/007 ,  H05K3/202 ,  H05K3/467 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2203/0152 ,  H05K2203/0769 ,  H05K2203/308 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/701 ,  Y10S977/724 ,  Y10S977/856 ,  Y10S977/857 ,  Y10T156/1052 ,  Y10T428/24802

Abstract: This invention provides free-standing structures, functionalized free-standing structures and functional devices that are flexible, including nano- and micromachined flexible fabrics comprising woven networks and mesh networks. The present invention provides processing methods for making and functionalizing flexible free-standing structures having a wide range of integrated materials, devices and device components. The methods of the present invention are capable of providing large area functional electronic, optoelectronic, fluidic, and electromechanical devices and device arrays which exhibit good device performance in stretched, bent and/or deformed configurations. The method includes forming sacrificial layers (120. 150) under first and second patterned structural layers ( 130, 170). and removing the sacrificial layers to form a free-standing fabric (200) with interconnected structural elements that are independently displaceable.

Abstract translation: 本发明提供了独立结构，功能化独立结构和功能性装置，其是柔性的，包括纳米和微加工的柔性织物，其包括编织网络和网状网络。 本发明提供了制造和功能化具有广泛的一体化材料，装置和装置部件的柔性独立结构的加工方法。 本发明的方法能够提供在拉伸，弯曲和/或变形构造中表现出良好装置性能的大面积功能的电子，光电子，流体和机电装置和装置阵列。 该方法包括在第一和第二图案化结构层（130,170）下形成牺牲层（120. 150）。 以及去除所述牺牲层以形成具有独立可移位的互连结构元件的独立织物（200）。

公开(公告)号：WO2008147789A2

公开(公告)日：2008-12-04

申请号：PCT/US2008064291

申请日：2008-05-21

Applicant: HONEYWELL INT INC ,  DING ZHE ,  GUIHEEN JAMES VINCENT ,  SMITH PETER ,  PALMER BEN ,  HUANG HONGMIN

Inventor： DING ZHE ,  GUIHEEN JAMES VINCENT ,  SMITH PETER ,  PALMER BEN ,  HUANG HONGMIN

IPC: H01B1/02 ,  H01B1/04 ,  H01B1/22 ,  H01B1/24 ,  H05K1/09

CPC classification number: H01B1/02 ,  B82Y10/00 ,  G02F1/13439 ,  H01B1/04 ,  H01B1/22 ,  H01B1/24 ,  H05K1/097 ,  H05K3/0023 ,  H05K3/467 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2201/0317 ,  H05K2201/0329

Abstract: Transparent conductive materials, articles and films are described herein a) that are easily and efficiently produced, b) can be produced prior to application or in situ, c) are easily applied to surfaces and substrates or formed into articles, d) can be produced and used with materials and methods that are generally accepted by the flat panel display (FPD) industry, along with other industries that produce and utilize microelectronics, e) can be tailored to be photoimageable and patternable using accepted photolithography techniques, f) have superior optical properties and have superior film forming properties, including better adhesion to other adjacent layers, the ability to be laid down in very or ultra thin layers and the ability to remain transparent when laid down as thicker layers. Methods of producing and using these transparent conductive materials are also disclosed.

Abstract translation: 透明导电材料，制品和膜在本文中描述a）容易且有效地制备，b）可以在施用之前或原位制备，c）易于施加到表面和基材上或形成制品，d）可以生产 并且与使用平板显示器（FPD）行业普遍接受的材料和方法一起使用，以及生产和利用微电子的其他行业，e）可以使用公认的光刻技术来定制成可光成像和可图案化，f）具有优异的光学 性能并且具有优异的成膜性能，包括对其它相邻层的更好的附着力，在非常或超薄层中放置的能力以及当铺设成更厚的层时保持透明的能力。 还公开了制造和使用这些透明导电材料的方法。

公开(公告)号：WO2008026520A1

公开(公告)日：2008-03-06

申请号：PCT/JP2007/066478

申请日：2007-08-24

Applicant: 国立大学法人東北大学 ,  財団法人国際科学振興財団 ,  大見 忠弘

Inventor： 大見 忠弘

IPC: H05K3/46 ,  H01L21/312 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/024 ,  H05K3/467 ,  H05K3/4688 ,  H01L2924/00

Abstract: 　多層配線構造に含まれる第１の配線層と第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物を介在させる。第１の配線層における配線と第２の配線層における配線との間に導電接続体を設け、第１の配線層における所定の配線と第２の配線層における所定の配線との間に比誘電率が５以下の絶縁物熱伝導体を設ける。

Abstract translation: 平均相对介电常数不超过2.5的气体或绝缘材料插入在多层布线结构中包含的第一布线层和第二布线层之间。 导电连接器设置在第一布线层的布线和第二布线层的布线之间，并且相对介电常数不大于5的绝缘导热体布置在第一布线层的特定布线和 第二布线层的一定线。

公开(公告)号：WO2006081352A3

公开(公告)日：2007-04-19

申请号：PCT/US2006002775

申请日：2006-01-26

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MARCANIO JOSEPH A

Inventor： BRODY THOMAS P ,  MARCANIO JOSEPH A

IPC: H01L21/4763

CPC classification number: H01L21/768 ,  H01L21/6715 ,  H01L21/67173 ,  H01L21/67207 ,  H01L21/76802 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/1545

Abstract: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).

Abstract translation: 多层电子器件可以形成为在绝缘基板（212）上包括绝缘基板（212），第一蒸镀导体层（312），第一导体层上的第一蒸镀绝缘体层（314） 312），其中具有至少一个通孔（316）的第一绝缘体层（314）和在第一绝缘体层（314）的通孔（316）中的气相沉积导电填料（320）。 期望地，导电填料（320）沉积在第一绝缘体层（314）的通孔（316）中，使得与第一导体层（312）相对的导电填料（320）的表面与表面 与第一导体层（312）相对的第一绝缘体层（314）。

公开(公告)号：WO2005114720A2

公开(公告)日：2005-12-01

申请号：PCT/US2005/017224

申请日：2005-05-16

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  UNIVERSITY OF SOUTHERN CALIFORNIA ,  RODGER, Damien C. ,  HUMAYUN, Mark ,  TAI, Yu-Chong ,  WEILAND, James D.

Inventor： RODGER, Damien C. ,  HUMAYUN, Mark ,  TAI, Yu-Chong ,  WEILAND, James D.

IPC: H01L21/50

CPC classification number: H05K1/032 ,  A61N1/04 ,  A61N1/0543 ,  A61N1/0551 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/007 ,  H05K3/048 ,  H05K3/467 ,  H05K3/4682 ,  H05K2201/0179 ,  H05K2203/016

Abstract: Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

Abstract translation: 制造聚对二甲苯基电极阵列的方法，其包括下面的聚对二甲苯层，一个或多个图案化的电极层，包括导电材料如金属和一个或多个上覆的聚对二甲苯层。 将上覆的聚对二甲苯蚀刻掉或以其他方式处理，以暴露要进行刺激或记录的电极。 器件中的所有其他导电材料都被围绕它的两层聚对二甲苯从环境中吸收。

公开(公告)号：WO02068245A8

公开(公告)日：2004-06-10

申请号：PCT/EP0201896

申请日：2002-02-22

Applicant: LEONI AG ,  ZAHRADNIK FRANZ ,  HARTMANN ULI ,  GOETZ KNUTH ,  REICHINGER GERHARD

Inventor： ZAHRADNIK FRANZ ,  HARTMANN ULI ,  GOETZ KNUTH ,  REICHINGER GERHARD

IPC: B05D1/10 ,  B05D7/00 ,  B60R16/02 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/14 ,  H05K3/34 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/1266 ,  B60R16/0207 ,  H05K1/0284 ,  H05K1/118 ,  H05K3/0014 ,  H05K3/0058 ,  H05K3/102 ,  H05K3/14 ,  H05K3/3468 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/467 ,  H05K2201/09109 ,  H05K2203/0517 ,  H05K2203/107 ,  H05K2203/1344 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: The invention relates to a method for producing a moulded component (2A-2G) comprising an integrated conductor strip (10), wherein a conductor strip (10) is produced on a carrier component (4) particularly by flame injection or cold gas injection. The surface of the carrier component (4) is treated in a selective manner corresponding to a predetermined path of the conductor strip (10) so that the surface areas thereof have different adhesions. A germ layer is applied to the path of the conductor strip (10), whereupon the conductor strip (10) is subsequently placed thereon. It is therefore possible to produce a moulded component (2A-2G) comprising an integrated conductive strip mould in a very flexible and economical manner. In automobile industries, special requests from the clients can be met in a fast and efficient manner by altering the layout of the conductor strip.

Abstract translation: 在通过火焰喷涂或冷气体来喷涂导体轨道产生具有在特定的支承部件（4）的集成导体线路（10）的模制部件（2A-2G）的方法（10）被产生。 为此目的，支撑部件（4）的表面根据导体路径（10）的指定过程选择性地进行处理，以使得不同的密合性的表面区域。 在导体路径（10）被施加一籽晶层（26）的设置过程中，被施加到转，eingentiliche导体轨道（10）。 从而高度灵活和具有集成的电路图案的制造模具部件（2A-2G）具有成本效益是可能的。 特别是在汽车行业客户的特殊需求可以通过修改导线线路布局进行快速，轻松地完成。

公开(公告)号：WO02025709A2

公开(公告)日：2002-03-28

申请号：PCT/US2001/029575

申请日：2001-09-21

IPC: H01L21/02 ,  H01L23/522 ,  H01L27/06 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01L28/55 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0688 ,  H01L28/10 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/16 ,  H05K3/467 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/28 ,  Y10T428/2804 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract translation: 公开了用于在各种薄膜混合基板表面（0501）上制造高可靠性电容器（1011），电感器（1012）和多层互连（1013）（包括电阻器（1014））的系统和方法。 所公开的方法首先采用在衬底（0501）上沉积和图案化的薄金属层（0502）。 该薄图案层（0502）用于为上电极组件之间的电容器结构（0603）和互连（0604）提供两个下电极。 接下来，在薄的图案化层（0502）上沉积电介质层（0705），并且对电介质层（0705）进行图案化以将薄的图案化层的接触孔（0806）打开。 然后将上电极层（0907,0908,1009,1010）沉积并图案化在电介质（0705）的顶部。

公开(公告)号：WO1994019726A1

公开(公告)日：1994-09-01

申请号：PCT/US1994002185

申请日：1994-02-24

Applicant: CERIDIAN CORPORATION

Inventor： CERIDIAN CORPORATION ,  PAI, Deepak, Keshav

IPC: G03F09/00

CPC classification number: H05K3/0052 ,  H01L21/4846 ,  H05K3/0023 ,  H05K3/467 ,  H05K2201/09781 ,  H05K2201/2009

Abstract: The present invention is an apparatus and method for machining a laminate structure (10) to form a selected shape. The method includes forming a first layer (26) on a substrate (24). A first protective structure (12) is defined that is attached to each of the first layer (26) and the substrate (24). At least a portion of the protective structure (12) has the selected shape. The laminate structure (10) is then machined along the first protective structure (12) thereby forming at least a portion of a selected shape.

Abstract translation: 本发明是用于加工层压结构（10）以形成选定形状的装置和方法。 该方法包括在基底（24）上形成第一层（26）。 定义了附接到第一层（26）和基底（24）中的每一个的第一保护结构（12）。 保护结构（12）的至少一部分具有选定的形状。 然后，层压结构（10）沿着第一保护结构（12）加工，从而形成至少一部分所选形状。

公开(公告)号：WO1992017994A1

公开(公告)日：1992-10-15

申请号：PCT/SU1991000055

申请日：1991-04-01

Applicant: FILIAL VSESOJUZNOGO NAUCHNO-ISSLEDOVATELSKOGO ... ,  ADASKO, Vladimir Iosifovich ,  VARDENBURG, Arnold Kurtovich ,  EMELYANOV, Alexandr Lvovich ,  EMELYANOV, Viktor Lvovich ,  SELIVERSTOV, Lev Alexeevich ,  SLONIMSKY, Alexandr Davydovich ,  SKLYAROV, Nikolai Alexeevich ,  TIKHONOV, Vladimir Ivanovich ,  ROGOZHIN, Jury Fedorovich ,  PILIPOSIAN, Pogos Mkrtychevich

Inventor： FILIAL VSESOJUZNOGO NAUCHNO-ISSLEDOVATELSKOGO ...

IPC: H05K03/46

CPC classification number: H05K3/403 ,  H05K1/056 ,  H05K1/113 ,  H05K1/117 ,  H05K3/0023 ,  H05K3/4076 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/105 ,  H05K2203/1355

Abstract: A multilayer printed circuit board has a metal base (1) with openings (12), the surface of the base and the walls of the openings being covered with an insulation layer (8) obtained by means of applying and mechanical processing, in turn, on both sides, a coating of a powder epoxy composition. An insulation relief (16) of a photo sensitive composition is obtained on the insulation coating, which is then filled with a metal by vacuum deposition. Conductors (4) and contact points (5) of the layer (3) of conducting pattern are obtained by removing the metal from the protruding parts of the relief (16). Then insulation relief (18) is formed corresponding to the location of the contact points (11) and of the commutation bars (10) connecting the layers (3, 6) of the conducting patterns, and is covered with a metal layer. After the removal of the metal from the protruding parts an insulation layer (9) is obtained in which are located the commutation bars (10) and the contact points (11). Then an insulation relief (19) is formed corresponding to the configuration of the layer (6) of the conducting pattern, the metal is applied and mechanically processed so as to obtain conductors (7) with contact points (8) of the layer (6) of the conducting pattern.

Abstract translation: 多层印刷电路板具有带有开口（12）的金属基底（1），基底的表面和开口壁被覆盖有通过施加和机械加工获得的绝缘层（8） 在两面上涂布粉末环氧组合物。 在绝缘涂层上获得光敏组合物的绝缘浮雕（16），然后通过真空沉积用金属填充。 通过从浮雕（16）的突出部分去除金属，可获得导电图案层（3）的导体（4）和接触点（5）。 然后，相应于连接导电图案的层（3,6）的接触点（11）和换向条（10）的位置形成绝缘凸缘（18），并被金属层覆盖。 在从突出部分移除金属之后，获得其中位于换向棒（10）和接触点（11）的绝缘层（9）。 然后，与导电图案的层（6）的构造相对应地形成绝缘放电（19），金属被施加并机械处理，以获得具有层（6）的接触点（8）的导体（7） ）的导电图案。