公开(公告)号：WO01068311A1

公开(公告)日：2001-09-20

申请号：PCT/US2001/007580

申请日：2001-03-09

IPC: B23K20/00 ,  H01L21/60 ,  H01L21/603 ,  H05K3/32 ,  B23K31/02 ,  H05K1/16 ,  H05K3/34

CPC classification number: H01L23/522 ,  H01L21/76838 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/325 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A flip chip structure (10) is formed by mechanically interlocking joining surfaces of a first (12) and a second (14) element. The first element (12), which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element (14), which may for example be a substrate pad, is provided with asperities (16) into which the first element (12) deforms plastically under pressure to form the mechanical interlock.

Abstract translation: 通过机械地互锁第一（12）和第二（14）元件的接合表面来形成倒装芯片结构（10）。 可以是集成电路芯片上的凸块的第一元件（12）包括具有低屈服强度和高的失效延伸率的柔软的可变形材料。 第二元件（14）的表面（其可以例如是衬底垫）设置有凹凸（16），第一元件（12）在压力下塑性变形到其中以形成机械互锁。

公开(公告)号：WO01065610A1

公开(公告)日：2001-09-07

申请号：PCT/EP2001/001853

申请日：2001-02-19

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L29/92

CPC classification number: H01L23/5223 ,  H01L21/76838 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to produce an integrated component comprising an integrated metal-insulator-metal capacitor (7), a dielectric intermediate layer (11) and an upper electrode (12) are firstly deposited on a copper lower electrode (6) in such a manner that they cover the entire surface. The metal-insulator-metal capacitor (7) is subsequently structured with etch stop in the dielectric intermediate layer (11). The results in preventing short circuits between the upper electrode (12) and the lower electrode (6).

Abstract translation: 用于制造具有集成的金属 - 绝缘体 - 金属电容器（7）的集成装置是第一至下部电极（6），铜（11）的介电中间层，并在整个表面上的上电极（12）制成。 随后，将金属 - 绝缘体 - 金属电容器（7）的图案化与所述层间电介质层（11）中的蚀刻停止进行。 避免了上部电极（12）和下部电极（6）之间，从而短路。

公开(公告)号：WO01063652A1

公开(公告)日：2001-08-30

申请号：PCT/DE2001/000465

申请日：2001-02-07

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895

Abstract: A thin lower electrode layer (2) having an optimally protected capacitor dielectric (3) is produced and structured. A conventional metallization layer for strip conductors is placed thereon as an upper electrode (11) and structured. The capacitor dielectric can be deposited on a very even, preferably metallic surface (e.g. preferably TiN), sealed by a thin, preferably metallic layer (e.g. TiN) and protected so that it does not become thinned or damaged by other process steps.

Abstract translation: 它是由一个薄的下部电极层（2）得到最佳的保护电容器电介质（3）和结构化和其上的用于互连作为上部电极（11）和图案化的常规金属化提供。 电容器电介质从而可以在非常光滑的，优选金属表面（如TiN），并通过一薄的，也优选为金属层（诸如TiN）沉积之后沉积密封并保护，使得它不会被其它工艺步骤变薄或损坏的 ，

公开(公告)号：WO01001461A1

公开(公告)日：2001-01-04

申请号：PCT/DE2000/001979

申请日：2000-06-20

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/76838 ,  H01L27/10852 ,  H01L28/60

Abstract: The invention relates to a method of producing a structured layer, especially of producing a conductive structured layer. The inventive method comprises the following steps: a) providing a substrate that comprises at least one target zone (8) and at least one migration zone (5, 14); b) applying the layer material (9); and c) heat-treating said material so that the layer material (9) migrates from the migration zone (5, 14) to the target zone (8). The inventive method is characterized in that the layer material (9) that is often only difficult to etch does not have to be structured directly. The desired structure (10) of the layer is defined by the prestructurization of the substrate into a target zone and a migration zone and is produced in a self-organized manner by the migration of the layer material due to the heat-treatment.

Abstract translation: 根据本发明，用于生产结构化层，特别是用于制备导电结构化层的方法，提供了一种方法，包括以下步骤：提供（8）和至少一个迁移区（5，14）a）基材具有至少一个目标区域; b）该层状材料（9）是施加; 和c），使得迁移区（5,14）到目标区域（8）的薄片状材料（9）迁移进行热处理。 本发明的方法具有这样的困难往往可蚀刻层材料（9）不能直接图案化的优点。 该层的所期望的结构（10）由所述预结构化在目标区域的基板，和一个迁移区确定，并且由所述层材料的迁移，由于以自组织的方式热处理生成。

公开(公告)号：WO9959190A3

公开(公告)日：2000-04-06

申请号：PCT/US9910331

申请日：1999-05-12

Applicant: SEMITOOL INC

Inventor： STEVENS E HENRY ,  BERNER ROBERT W

IPC: H01L21/302 ,  C12N15/31 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L37/00 ,  H01L21/00 ,  B23K9/00 ,  C23C16/00 ,  H01L21/22 ,  H01L21/465 ,  H01L21/48 ,  H01L37/32

CPC classification number: H01L21/76885 ,  H01L21/32134 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76838

Abstract: A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.

Abstract translation: 公开了一种半导体制造工具配置和用于将一个或多个级别的互连金属化应用于半导体工件的大致平面的电介质表面的相应工艺，其具有工具组之间的最小数量的工件传送操作。

公开(公告)号：WO99060829A2

公开(公告)日：1999-11-25

申请号：PCT/US1999/010502

申请日：1999-05-12

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L51/40 ,  H05K1/16 ,  H05K3/04 ,  H05K3/12 ,  H05K3/46

CPC classification number: H05K3/1275 ,  H01L21/4867 ,  H01L21/76838 ,  H01L23/49855 ,  H01L51/0022 ,  H01L2224/16225 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3011 ,  H05K1/16 ,  H05K3/046 ,  H05K3/1241 ,  H05K3/1266 ,  H05K3/4664 ,  H05K2203/0113 ,  H05K2203/0517 ,  H05K2203/1545 ,  H01L2924/00

Abstract: A printer (108) forms conductive traces (116) on the print media (114) for circuit connection, such as for connecting to integrated circuit chips. The printer (108) prints the conductive traces (116) according to a digital representation of a desired conductor pattern (112) produced with a computer system (102), thus eliminating typical masking and photolithographic steps. In one embodiment, the printer (108) includes three print heads in series and a transport mechanism that transport the print media past the print heads to print conductive, dielectric, and/or ferromagnetic inks. In another embodiment, the printer includes a single print head that sequentially prints each of the inks. By printing not only conductive material, the printer (108) can print various impedance elements, including resistors, capacitors, and inductors. The printer can also print N- and P-type material to produce active circuit elements. The printer can print various other electrical devices, all in a very inexpensive manner.

Abstract translation: 打印机（108）在打印介质（114）上形成用于电路连接的导电迹线（116），例如用于连接到集成电路芯片。 打印机（108）根据由计算机系统（102）产生的期望的导体图案（112）的数字表示打印导电迹线（116），从而消除典型的掩模和光刻步骤。 在一个实施例中，打印机（108）包括串联的三个打印头和传送打印介质经过打印头以打印导电，电介质和/或铁磁油墨的传送机构。 在另一个实施例中，打印机包括顺序地打印每个墨水的单个打印头。 通过印刷不仅导电材料，打印机（108）可以打印各种阻抗元件，包括电阻器，电容器和电感器。 打印机还可以打印N型和P型材料以产生有源电路元件。 打印机可以以非常便宜的方式打印各种其他电气设备。

公开(公告)号：WO99059204A1

公开(公告)日：1999-11-18

申请号：PCT/US1999/010369

申请日：1999-05-11

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs (54, 56; 56, 58) are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, each of which being covered with different first and second (66) insulating materials. An opening (68) is etched through one of the first and second (54, 56; 56, 58) insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material (70) is formed within the opening (68) and in electrical connection with the one plug (54, 58). In a preferred embodiment, two-spaced apart conductive lines (26) are formed over a substrate and conductive plugs (54, 56, 58) are formed between, and on each side of the conductive lines (26). The conductive plug formed between the conductive lines provides a bit line contact plug (56) having an at least partially exposed top portion (60). The exposed top portion is encapsulated with a first insulating material (50, 62). A layer of second different insulating material (66) is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs (54, 58) on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

Abstract translation: 描述了与导电插塞电接触的方法，形成接触开口的方法，以及形成动态随机存取存储器电路的方法。 在一个实施例中，一对导电接触插塞（54,56; 56,58）形成为相对于半导体晶片向外突出。 插头具有各自的顶部，每个顶部被不同的第一和第二（66）绝缘材料覆盖。 通过第一和第二（54,56,56,58）绝缘材料中的一个蚀刻开口（68），以仅露出一对插头中的一个顶部。 导电材料（70）形成在开口（68）内并与一个插头（54,58）电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线（26），并且在导线（26）的每一侧之间和之间形成导电插塞（54,56,58）。 形成在导线之间的导电插塞提供了具有至少部分暴露的顶部部分（60）的位线接触插头（56）。 暴露的顶部被第一绝缘材料（50,62）封装。 在衬底上形成第二不同绝缘材料层（66）。 在导电线的每一侧上的导电插塞（54,58）上相对于第一绝缘材料选择性地去除部分第二绝缘材料，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：WO9910916A3

公开(公告)日：1999-08-05

申请号：PCT/US9817276

申请日：1998-08-20

Applicant: MICRON TECHNOLOGY INC

Inventor： ROBINSON KARL ,  TAYLOR TED

IPC: C23C18/18 ,  C23C18/40 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  C23C18/16

CPC classification number: H01L21/76838 ,  H01L21/288 ,  H01L21/76879 ,  H01L21/76885 ,  Y10S438/903 ,  Y10S438/945 ,  Y10S438/976

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract translation: 提供了一种在衬底的含钛表面上沉积铜的方法。 该方法包括在衬底上形成图案化的催化剂材料，使得含钛表面暴露在选定的区域中。 该催化剂材料具有大于二氧化钛还原半反应电位大小的氧化半反应电位。 铜然后从无电解溶液沉积到含钛表面的暴露区域上。

公开(公告)号：WO99025020A1

公开(公告)日：1999-05-20

申请号：PCT/EP1998/007231

申请日：1998-11-11

IPC: B81C99/00 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/78 ,  H01L21/82

CPC classification number: B23K26/0057 ,  B23K26/40 ,  B23K2203/172 ,  H01L21/76254 ,  H01L21/76838 ,  H01L21/7806 ,  H01L29/66772

Abstract: The invention relates to a method for producing integrated circuits and components. Previously, substrates were initially made thinner or thin layers were produced according to various methods in order to produce integrated circuits on thin semiconductor layers. Integrated circuits were subsequently produced in a separate process. The inventive method is designed to produce integrated circuits on thin semiconductor layers using traditional wafers as a starting material. A step modifying the quality of the substrate in a layer underneath the components and a step separating the layer containing said components from the rest of the substrate are added at an appropriate stage to known steps in the production of integrated circuits on a substrate. The method can be used especially in silicon CMOS technology. It enables the substrate that is used as a starting material to be re-used. The inventive method also enables individual chips to be detached from the wafer.

Abstract translation: 提供了一种用于制造集成电路和元件的方法。 基板最初被减薄或通过用于制造在薄半导体层的集成电路的各种方法装置产生薄层。 生产集成电路的是在一个单独的处理随后执行。 该新方法应该允许生产上的薄半导体层集成电路，在作为起始材料的常规的晶片被使用。 在已知的步骤，以产生改变衬底材料的性质在下面的部件的层和分离含有层中的成分的步骤的一个步骤中，从衬底的其余部分插入在合适的位置的基板上的集成电路。 该方法可特别是在硅CMOS技术中使用。 它允许用作起始材料的衬底的可重用性。 此外，它允许从晶片更换单独的芯片。

公开(公告)号：WO98054377A2

公开(公告)日：1998-12-03

申请号：PCT/US1998/010789

申请日：1998-05-27

IPC: C23C14/00 ,  C23C14/06 ,  C23C14/14 ,  C23C14/16 ,  C23C14/34 ,  C23C14/35 ,  C23C14/58 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

CPC classification number: C23C14/345 ,  C23C14/0036 ,  C23C14/0641 ,  C23C14/16 ,  C23C14/3492 ,  C23C14/358 ,  C23C14/5833 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: We have discovered that the residual stress residing in a tantalum (Ta) film or a tantalum nitride (TaNx, where 0 dynes/cm (tensile stress) to about -2 x 10 dynes/cm (compressive stress), depending on the process variables described above. Tantalum nitride (TaNx) films deposited using the IMP method typically can be tuned to exhibit a residual stress within the same range as that specified above with reference to Ta films. We have been able to reduce the residual stress in either the Ta or TaNx films to range between about 6 x 10 dynes/cm and about -6 x 10 dynes/cm using tuning techniques described herein. The Ta and TaNx films can also be tuned subsequent to deposition using ion bombardment of the film surface and annealing of the deposited film. Barrier performance of the films can be improved by depositing the films at a substrate temperature of at least 300 DEG C.

Abstract translation: 我们已经发现，通过在膜的沉积期间控制特定的工艺变量，可以控制（调整）驻留在钽（Ta）膜或氮化钽（TaNx，其中0 （压缩应力），取决于上述过程变量。 使用IMP方法沉积的钽氮化物（TaNx）膜通常可以被调整以在与上述参考Ta膜所规定的相同范围内显示残余应力。 我们已经能够将Ta或TaNx膜中的残余应力减小到约6×10 9达因/ cm 2和约-6×10 9达因/ cm 2之间的范围，使用 调谐技术。 Ta和TaNx膜也可以在沉积后利用膜表面的离子轰击和沉积膜的退火进行调整。 可以通过在至少300℃的衬底温度下沉积膜来改善膜的阻隔性能。