公开(公告)号：WO2009141402A1

公开(公告)日：2009-11-26

申请号：PCT/EP2009/056183

申请日：2009-05-20

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  COFFY, Romain

Inventor： COFFY, Romain

IPC: G01R31/28 ,  G01R1/20 ,  H01L21/66 ,  H01L23/485

CPC classification number: G01R31/2884 ,  G01R1/0408 ,  G01R31/2822 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit (1), a passivation layer (19) comprising openings at the level of metal tracks (17) of the last interconnect stack of the integrated circuit; forming, in the openings, first pads (11) connected to second pads (13) formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

Abstract translation: 一种用于制造和测试集成电路的方法，包括以下步骤：在集成电路（1）的上部形成钝化层（19），该钝化层包括位于最后互连的金属轨道（17）的开口处的开口 堆叠的集成电路; 在所述开口中形成通过导电轨道部分连接到形成在所述钝化层上的第二焊盘（13）的第一焊盘（11），所述第一焊盘用于连接所述集成电路; 通过将测试头与第二个焊盘接触来测试集成电路; 以及消除所述导电轨道部分中的至少一个的至少一部分。

公开(公告)号：WO2010112983A1

公开(公告)日：2010-10-07

申请号：PCT/IB2009/053463

申请日：2009-03-31

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  COFFY, Romain ,  SAUTY, Jean-François

Inventor： COFFY, Romain ,  SAUTY, Jean-François

IPC: H01L23/49

CPC classification number: H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/274 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01202 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/20752 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2924/01204 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The invention concerns a semiconductor package comprising a semiconductor die (3) attached to a support (2) having electrically conductive paths, (6) said semiconductor die having a bond-pad (4) electrically connected to an electrically conductive path (6) on said support by a wire-bond (7) of a first metallic composition, such as an alloy of copper, said wire-bond and said bond-pad being coated with a protection layer (40) of a second metallic composition, such as an alloy of nickel.

Abstract translation: 本发明涉及一种半导体封装，其包括连接到具有导电路径的支撑体（2）的半导体管芯（3），（6）所述半导体管芯具有电连接到导电路径（6）上的接合焊盘（4） 所述支撑体通过第一金属组合物（例如铜合金）的引线键合（7），所述引线接合和所述接合焊盘涂覆有第二金属组合物的保护层（40），例如 镍合金。

公开(公告)号：WO2010069786A1

公开(公告)日：2010-06-24

申请号：PCT/EP2009/066441

申请日：2009-12-04

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  COFFY, Romain ,  SAUTY, Jean-François

Inventor： COFFY, Romain ,  SAUTY, Jean-François

IPC: H05K9/00 ,  H01L23/552 ,  H05K1/02

CPC classification number: H05K9/0022 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/284 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/09872 ,  Y10T29/49124 ,  H01L2224/81 ,  H01L2924/00

Abstract: A surface-mounted shielded multicomponent assembly, comprising a wafer (1) on which several electronic components (2, 3, 4) are assembled; an insulating layer (30) conformally deposited on the structure with a thickness smaller than the height of the electronic components, comprising at least one opening (31) emerging on a contact (32) of said wafer; a conductive shielding layer (35) covering the insulating layer and said at least one opening; and a resin layer (6) covering the conductive layer.

Abstract translation: 一种表面安装的屏蔽多组件组件，包括其上组装有几个电子部件（2,3,4）的晶片（1） 在所述结构上共形沉积的厚度小于所述电子部件的高度的绝缘层（30），包括在所述晶片的触点（32）上露出的至少一个开口（31） 覆盖绝缘层和所述至少一个开口的导电屏蔽层（35）; 和覆盖导电层的树脂层（6）。

公开(公告)号：WO2010057808A1

公开(公告)日：2010-05-27

申请号：PCT/EP2009/064918

申请日：2009-11-10

Applicant: STMicroelectronics (GRENOBLE) SAS ,  STMicroelectronics S.r.l. ,  COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

Inventor： COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

IPC: H01L25/16 ,  H01L23/538 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/0401

Abstract: A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

Abstract translation: 半导体器件包括至少一个第一部件（5）（例如，第一集成电路），其具有设置有电连接焊盘的正面。 第一部件嵌入在支撑层（2）中，是使得第一部件的前表面不被覆盖并平行于支撑层的第一面的位置。 在第一部件的正面和支撑层的第一面上形成中间层（8）。 中间层内的电连接网络（9）选择性地连接到第一部件的电连接焊盘。 该装置还包括至少一个第二部件（11）（例如，第二集成电路，其中一个面放置在中间层的上方，并且具有选择性地连接到电连接网络的电连接焊盘）。电连接通孔（17）通过 通过支撑层并且将电连接网络选择性地连接到形成在支撑层的第二面上的外部电连接。

公开(公告)号：WO2009027132A1

公开(公告)日：2009-03-05

申请号：PCT/EP2008/058239

申请日：2008-06-27

Applicant: STMicroelectronics (Grenoble) SAS ,  COFFY, Romain ,  SEILLER, Jacky ,  PROVENT, Gil

Inventor： COFFY, Romain ,  SEILLER, Jacky ,  PROVENT, Gil

IPC: H05K3/24 ,  H05K3/34

CPC classification number: H05K3/3473 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/014 ,  H01L2924/12036 ,  H05K2203/043 ,  H05K2203/0574 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: Method for fabricatingelectrical bonding pads of a wafer Method for fabricatingelectrical bonding pads on the electrical contact areas of a wafer, comprising the productionof first blocks (7) made of a solder material, the productionof second blocks(10) made of a solder material on these first blocks, and passage through an oven so as to shape the said blocks into approximately domed electrical bonding pads.

Abstract translation: 用于制造晶片的电接合焊盘的方法用于在晶片的电接触区域上制造电接合焊盘的方法，包括制造由焊料材料制成的第一块（7），在其上制造由焊料材料制成的第二块（10） 第一块，并通过烘箱，以便将所述块形成为大致圆顶形的电焊盘。