公开(公告)号：WO2013101423A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/068087

申请日：2012-12-06

Applicant: APPLIED MATERIALS, INC. ,  HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  XUAN, Guangchi ,  ZHOU, Jianhua ,  LI, Jigang ,  SHAIKH, Shahid ,  REILLY, Patrick ,  NOWAK, Thomas ,  ROCHA-ALVAREZ, Juan Carlos ,  PARK, Heung Lak ,  KIM, Bok Hoen

Inventor： HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  XUAN, Guangchi ,  ZHOU, Jianhua ,  LI, Jigang ,  SHAIKH, Shahid ,  REILLY, Patrick ,  NOWAK, Thomas ,  ROCHA-ALVAREZ, Juan Carlos ,  PARK, Heung Lak ,  KIM, Bok Hoen

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/66833 ,  C23C16/24 ,  C23C16/345 ,  C23C16/401 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L27/11582 ,  H01L29/7926

Abstract: Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550 °C; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600 °C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700 °C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods.

Abstract translation: 提供了用于通过在大于约550℃的牺牲膜沉积温度下沉积牺牲氮化物膜层来沉积用于3D存储器件的垂直栅极中的薄膜层堆叠的方法; 在氧化物沉积温度约600℃下在氮化物膜层上沉积氧化膜层。 或更大; 重复上述步骤以沉积具有交替层的牺牲膜和氧化物膜的膜堆叠; 在薄膜叠层中形成多个孔; 以及在约700℃的多晶硅工艺温度下在所述膜堆叠中的多个孔中沉积多晶硅。 或更大，其中牺牲膜层和氧化物膜层在多晶硅沉积期间经历接近零收缩。 也可以通过这些方法制造闪存驱动器存储器件。

公开(公告)号：WO2012087613A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/064179

申请日：2011-12-09

Applicant: APPLIED MATERIALS, INC. ,  RAJAGOPALAN, Nagarajan ,  PARK, Ji Ae ,  YAMASE, Ryan ,  PATEL, Shamik ,  NOWAK, Thomas ,  XIA, Li-Qun ,  KIM, Bok Hoen ,  DING, Ran ,  BALDINO, Jim ,  NAIK, Mehul ,  RAMASWAMI, Sesh

Inventor： RAJAGOPALAN, Nagarajan ,  PARK, Ji Ae ,  YAMASE, Ryan ,  PATEL, Shamik ,  NOWAK, Thomas ,  XIA, Li-Qun ,  KIM, Bok Hoen ,  DING, Ran ,  BALDINO, Jim ,  NAIK, Mehul ,  RAMASWAMI, Sesh

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/045 ,  H01L23/055

CPC classification number: H01L24/13 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/6835 ,  H01L21/68792 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/742 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00

Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

Abstract translation: 一种硅通孔制造方法包括蚀刻硅板中的多个通孔。 在硅板的表面和通孔的侧壁和底壁上沉积氧化物衬垫。 然后将金属导体沉积在通孔中。 在可与氧化物衬垫同时使用的另一种方案中，氮化硅钝化层沉积在衬底的硅板的暴露后表面上。

公开(公告)号：WO2011068711A2

公开(公告)日：2011-06-09

申请号：PCT/US2010/057670

申请日：2010-11-22

Applicant: APPLIED MATERIALS, INC. ,  HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  PARK, Ji, Ae ,  MEBARKI, Bencherki ,  PARK, Heung, Lak ,  KIM, Bok, Hoen

Inventor： HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  PARK, Ji, Ae ,  MEBARKI, Bencherki ,  PARK, Heung, Lak ,  KIM, Bok, Hoen

IPC: H01L29/868

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L29/66136 ,  H01L29/868

Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

Abstract translation: 描述了在衬底上形成高电流密度垂直p-i-n二极管的方法。 该方法包括同时组合含有IV族元素的前体和以任何顺序依次暴露于n型掺杂剂前体和p型掺杂剂前体的步骤。 通过在流动含IV族元素的前体的同时减少或消除掺杂剂前体的流动，在N型层和P型层之间沉积本征层。 在沉积n型层，本征层和p型层中的每一个期间，衬底可以位于相同的处理室中，并且衬底不暴露于相邻层的沉积之间的大气。

公开(公告)号：WO2023028007A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/041091

申请日：2022-08-22

Applicant: APPLIED MATERIALS, INC.

Inventor： RATHI, Sudha ,  BALASUBRAMANIAN, Ganesh ,  RAJAGOPALAN, Nagarajan ,  KHAJA, Adbul Aziz ,  PARA, Prashanthi ,  TAILOR, Hiral D.

IPC: H01L21/02 ,  C23C16/26 ,  C23C16/50 ,  C23C16/56

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.

公开(公告)号：WO2021026283A1

公开(公告)日：2021-02-11

申请号：PCT/US2020/045087

申请日：2020-08-06

Applicant: APPLIED MATERIALS, INC.

Inventor： HAN, Xinhai ,  YU, Hang ,  HU, Kesong ,  ENSLOW, Kristopher ,  OGATA, Masaki ,  WANG, Wenjiao ,  WANG, Chuan Ying ,  YANG, Chuanxi ,  MAHER, Joshua ,  LEONG, Phaik Lynn ,  TEONG, Qi En ,  JAIN, Alok ,  RAJAGOPALAN, Nagarajan ,  PADHI, Deenesh

IPC: H01L21/22 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/11582

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at.%. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

公开(公告)号：WO2012047697A2

公开(公告)日：2012-04-12

申请号：PCT/US2011/053730

申请日：2011-09-28

Applicant: APPLIED MATERIALS, INC. ,  RAJAGOPALAN, Nagarajan ,  HAN, Xinhai ,  PARK, J, Ae ,  KIYOHARA, Tsutomu ,  PARK, Sohyun ,  KIM, Bok, Hoen

Inventor： RAJAGOPALAN, Nagarajan ,  HAN, Xinhai ,  PARK, J, Ae ,  KIYOHARA, Tsutomu ,  PARK, Sohyun ,  KIM, Bok, Hoen

IPC: H01L21/205

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234

Abstract: A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.

Abstract translation: 在保持真空的同时，在单个等离子体增强化学气相沉积处理室中将不同材料的叠层沉积在衬底上。 衬底被放置在处理室中，并且第一处理气体被用于在衬底上形成第一材料的第一层。 在使用第二处理气体在衬底上形成第二材料的第二层之前执行等离子体吹扫和气体吹扫。 重复进行等离子体吹扫和气体吹扫，并将第一和第二材料的附加层沉积在层叠上。

公开(公告)号：WO2011115997A2

公开(公告)日：2011-09-22

申请号：PCT/US2011/028531

申请日：2011-03-15

Applicant: APPLIED MATERIALS, INC. ,  RAJAGOPALAN, Nagarajan ,  HAN, Xinhai ,  YAMASE, Ryan ,  PARK, Ji Ae ,  PATEL, Shamik ,  NOWAK, Thomas ,  CUI, Zhengjiang ,  NAIK, Mehul ,  PARK, Heung Lak ,  DING, Ran ,  KIM, Bok Hoen

Inventor： RAJAGOPALAN, Nagarajan ,  HAN, Xinhai ,  YAMASE, Ryan ,  PARK, Ji Ae ,  PATEL, Shamik ,  NOWAK, Thomas ,  CUI, Zhengjiang ,  NAIK, Mehul ,  PARK, Heung Lak ,  DING, Ran ,  KIM, Bok Hoen

IPC: H01L21/318 ,  H01L21/60

CPC classification number: H01L21/02068 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/56 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/11831 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1358 ,  H01L2224/13583 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.

Abstract translation: 描述了在衬底的特征上形成包括氮化硅的钝化层的方法。 在沉积方法的第一阶段中，将包含含硅气体和含氮气体的介电沉积气体引入工艺区域并通电以沉积氮化硅层。 在第二阶段中，将具有不同于介电沉积气体的组成不同的处理气体引入处理区并通电以处理氮化硅层。 第一和第二阶段可以执行多次。

公开(公告)号：WO2006050482A3

公开(公告)日：2006-05-11

申请号：PCT/US2005/039899

申请日：2005-11-03

Applicant: APPLIED MATERIALS, INC. ,  RAJAGOPALAN, Nagarajan ,  XIA, Li-qun ,  BALSEANU, Mihaela ,  NOWAK, Thomas ,  SHAH, Ranjana ,  XU, Huiwen ,  PETERSON, Chad ,  WITTY, Derek R. ,  M'SAAD, Hichem

Inventor： RAJAGOPALAN, Nagarajan ,  XIA, Li-qun ,  BALSEANU, Mihaela ,  NOWAK, Thomas ,  SHAH, Ranjana ,  XU, Huiwen ,  PETERSON, Chad ,  WITTY, Derek R. ,  M'SAAD, Hichem

IPC: C23C16/44

Abstract: A method for seasoning a deposition chamber wherein the chamber components and walls are densely coated with a material that does not contain carbon prior to deposition of an organo-silicon material on a substrate. An optional carbon-containing layer may be deposited therebetween. A chamber cleaning method using low energy plasma and low pressure to remove residue from internal chamber surfaces is provided and may be combined with the seasoning process.

公开(公告)号：WO2005109473A3

公开(公告)日：2005-11-17

申请号：PCT/US2005/013313

申请日：2005-04-19

Applicant: APPLIED MATERIALS, INC. ,  RAJAGOPALAN, Nagarajan ,  SHEK, Meiyee ,  LEE, Albert ,  LAKSHMANAN, Annamalai ,  XIA, Li-Qun ,  CUI, Zhenjiang

Inventor： RAJAGOPALAN, Nagarajan ,  SHEK, Meiyee ,  LEE, Albert ,  LAKSHMANAN, Annamalai ,  XIA, Li-Qun ,  CUI, Zhenjiang

IPC: H01L21/768

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed on a substrate surface, exposing the substrate surface to a reducing compound, a silicon based compound, or both, reacting at least a portion of the substrate surface with the reducing compound, the silicon based compound, or both, and depositing a silicon carbide layer without breaking vacuum.

公开(公告)号：WO2016111798A1

公开(公告)日：2016-07-14

申请号：PCT/US2015/064684

申请日：2015-12-09

Applicant: APPLIED MATERIALS, INC.

Inventor： TSIANG, Michael Wenyoung ,  JHA, Praket P. ,  HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  KIM, Bok Hoen ,  KIYOHARA, Tsutomu ,  SREEKALA, Subbalakshmi

IPC: H01L21/027

CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L27/11582

Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

Abstract translation: 本公开的实施例提供了在半导体衬底上制造具有最小光刻重叠误差的膜层的方法和系统。 在一个实施例中，在衬底上形成膜层的方法包括将包含含硅气体和反应气体的沉积气体混合物供给到设置在处理室中的衬底支撑体上的衬底上，在存在 在处理室中沉积气体混合物，将电流施加到设置在处理室中的等离子体轮廓调制器，同时将沉积气体混合物供应到处理室中，以及在衬底上沉积膜层的同时旋转衬底。