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    FRONT-END PROCESSED WAFER HAVING THROUGH-CHIP CONNECTIONS
    2.
    发明申请
    FRONT-END PROCESSED WAFER HAVING THROUGH-CHIP CONNECTIONS 审中-公开
    具有通过芯片连接的前端加工的波形

    公开(公告)号：WO2008122889A2

    公开(公告)日：2008-10-16

    申请号：PCT/IB2008/001429

    申请日：2008-06-05

    Applicant: CUFER ASSET LTD. L.L.C. ,  TREZZA, John

    Inventor： TREZZA, John

    CPC classification number: H01L21/76898 ,  B81C1/00095

    Abstract: A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

    Abstract translation: 一种方法包括在装有器件的半导体晶片中形成通孔，使装置的半导体晶片中的至少一些通孔导电，以及对装置的半导体晶片进行后端处理，以便在 导电通孔和金属化层。 一种替代方法包括在装置轴承半导体晶片中形成通孔，使装置中的半导体晶片中的至少一些通孔导电，以及处理装置的半导体晶片，以便在导电通孔 和导电半导体层。

    CONDUCTIVE VIA FORMATION
    4.
    发明申请
    CONDUCTIVE VIA FORMATION 审中-公开
    导致形成

    公开(公告)号：WO2008129423A2

    公开(公告)日：2008-10-30

    申请号：PCT/IB2008/001612

    申请日：2008-06-19

    Applicant: CUFER ASSET LTD. L.L.C. ,  TREZZA, John

    Inventor： TREZZA, John

    IPC: C23C18/16 ,  C23C18/18 ,  C23C18/31 ,  C25D5/02 ,  C25D7/12

    CPC classification number: C25D5/02 ,  C23C18/1603 ,  C23C18/165 ,  C23C18/1653 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76898 ,  H01L2221/1089

    Abstract: A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10µm and a depth of greater than about 50µm, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal.

    Abstract translation: 一种方法包括使用沉积技术将第一导电材料沉积到材料中形成的通孔中，该通孔在材料表面的直径小于约10μm，深度大于约50μm，因此 在通孔内形成种子层，然后通过用第二导电材料无电地电镀种子层而在通孔形成和产生增厚层之间的通孔内进行任何活化过程，在种子层的顶部上产生增厚层， 然后将导体金属电镀到增稠层上，直到通孔内的增稠层界定的体积被导体金属填充。

    ULTRA-THIN STACKED CHIOS PACKAGING
    5.
    发明申请
    ULTRA-THIN STACKED CHIOS PACKAGING 审中-公开

    公开(公告)号：WO2008129424A3

    公开(公告)日：2008-10-30

    申请号：PCT/IB2008/001626

    申请日：2008-06-20

    Applicant: CUFER ASSET LTD. L.L.C. ,  TREZZA, John

    Inventor： TREZZA, John

    IPC: H01L21/98 ,  H01L25/065 ,  H01L21/68

    Abstract: A packaging method involves attaching a first chip (1002) to a stable base' (600), forming contact pads (902) at locations on the stable base, applying a planarizing medium (1102) onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths (1302, 1304) on the medium, attaching a second chip (1402) to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material (1502) on top of the planarizing medium.

    VARIABLE OFF-CHIP DRIVE
    7.
    发明申请
    VARIABLE OFF-CHIP DRIVE 审中-公开
    可变的片外驱动

    公开(公告)号：WO2008101095A2

    公开(公告)日：2008-08-21

    申请号：PCT/US2008/053986

    申请日：2008-02-14

    Applicant: CUBIC WAFER, INC. ,  WYMAN, Theodore, J. ,  TREZZA, John

    Inventor： WYMAN, Theodore, J. ,  TREZZA, John

    IPC: H03K19/0185

    CPC classification number: H03K19/018585

    Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.

    Abstract translation: 驱动器电路包括一组可选择的驱动器，每个驱动器具有单独的驱动能力，所述驱动器可选择使得i）当驱动器的子集被选择时，驱动器将以第一驱动级别驱动信号，以及ii） 当驱动器的子集和至少一个额外的驱动器被选择时，由至少一个附加驱动器所提供的驱动级别的驱动器将驱动器的驱动程度大于第一级别的级别。

    ROUTINGLESS CHIP ARCHITECTURE
    8.
    发明申请
    ROUTINGLESS CHIP ARCHITECTURE 审中-公开

    公开(公告)号：WO2006138490A3

    公开(公告)日：2006-12-28

    申请号：PCT/US2006/023362

    申请日：2006-06-14

    Applicant: CUBIC WAFER, INC. ,  TREZZA, John ,  MISRA, Abhay

    Inventor： TREZZA, John ,  MISRA, Abhay

    IPC: H01L21/44

    Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back- end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

    MULTI-PIECE FIBER OPTIC COMPONENT AND MANUFACTURING TECHNIQUE
    9.
    发明申请
    MULTI-PIECE FIBER OPTIC COMPONENT AND MANUFACTURING TECHNIQUE 审中-公开
    多片纤维光学元件和制造技术

    公开(公告)号：WO2003003068A2

    公开(公告)日：2003-01-09

    申请号：PCT/US2002/022092

    申请日：2002-06-28

    Applicant: XANOPTIX, INC. ,  TREZZA, John ,  KANG, Keith ,  DUDOFF, Greg ,  OLSON, Ronald

    Inventor： TREZZA, John ,  KANG, Keith ,  DUDOFF, Greg ,  OLSON, Ronald

    IPC: G02B

    CPC classification number: G02B6/4249 ,  G02B6/12002 ,  G02B6/138 ,  G02B6/32 ,  G02B6/3644 ,  G02B6/3692 ,  G02B6/38 ,  G02B6/3834 ,  G02B6/3885 ,  G02B6/42

    Abstract: A commercial fiber optic connector of a style constructed to accept a ferrule-like unit therein has optical fibers, each having a first part and a second part separated by lengths, a low precision piece having a peripheral shape of a part of the ferrule like unit, two high precision slices each having fiber holes therein. A chamber separates the two high precision pieces defining a volume therebetween. The optical fibers have their first parts within the fiber holes in one of the high precision slices, their second parts within the fiber holes in the other of the high precision slices, and at least some of their length within the volume. The low precision piece and the two high precision slices collectively form the ferrule like unit and the ferrule like unit is contained substantially within the connector housing. A method of making a commercial optical connector involves making a first plate having holes, each larger than a cross sectional area of an optical fiber; making a second plate having holes each larger than the cross sectional area of the optical fiber; inserting an optical fiber in one of the holes in the first plate and one of the holes in the second plate, forming a ferrule component by connecting each of the first plate and the second plate to a chamber that separates the first plate from the second plate, and inserting the ferrule component in a ferrule location of the commercial optical connector.

    Abstract translation: 被构造成在其中接纳套圈状单元的样式的商用光纤连接器具有光纤，每个光纤具有分开的长度的第一部分和第二部分，具有外围形状的低精度件 套箍状单元的一部分，两个高精度片中的每一个都具有纤维孔。 腔室将两个高精度部件分隔开，从而在两者之间限定体积。 光纤的第一部分在高精度切片之一的纤维孔内，第二部分在另一个高精度切片的纤维孔内，并且其至少一部分长度在体积内。 低精度部件和两个高精度切片共同形成套圈状单元，并且套圈状单元基本上包含在连接器壳体内。 一种制造商用光连接器的方法涉及制造具有孔的第一板，每个孔都大于光纤的横截面积; 制作具有比光纤的横截面积大的孔的第二板; 将光纤插入第一板中的一个孔中和第二板中的一个孔中，通过将第一板和第二板中的每一个连接至将第一板与第二板分隔开的腔室来形成套箍部件 并将套管部件插入商用光连接器的套圈位置。

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