公开(公告)号：WO2015026344A1

公开(公告)日：2015-02-26

申请号：PCT/US2013/056058

申请日：2013-08-21

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  GUZEK, John S. ,  SANKMAN, Robert L.

Inventor： TEH, Weng Hong ,  GUZEK, John S. ,  SANKMAN, Robert L.

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/8203 ,  H01L2224/82031 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/18162

Abstract: Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例针对集成电路（IC）封装组件中的嵌入式硅管芯的无扰动接口。 在一个实施例中，一种方法包括在其中形成限定空腔的电介质材料的周围部分; 将至少一个模具放置在所述空腔中，所述模具包括接触件; 在模具和周围部分上沉积电介质材料; 蚀刻介电材料以暴露接触; 并将导电材料沉积到触点上。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2013089754A1

公开(公告)日：2013-06-20

申请号：PCT/US2011/065269

申请日：2011-12-15

Applicant: INTEL CORPORATION ,  MALATKAR, Pramod ,  TEH, Weng Hong ,  GUZEK, John S. ,  SANKMAN, Robert L.

Inventor： MALATKAR, Pramod ,  TEH, Weng Hong ,  GUZEK, John S. ,  SANKMAN, Robert L.

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Abstract translation: 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：WO2013101156A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068034

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  SANKMAN, Robert L.

Inventor： TEH, Weng Hong ,  SANKMAN, Robert L.

IPC: H01L23/48

CPC classification number: B81B7/0006 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00134 ,  B81C1/0023 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16135 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2224/82

Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.

Abstract translation: 一种包括模具的装置，包括第一侧和相对的第二侧，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的第二侧的积聚载体，所述堆积载体包括导电材料和绝缘材料的多个交替层，其中所述导电材料层中的至少一个耦合到所述接触点之一 的死亡 并且所述积聚载体内的至少一个装置设置在无图案化的导电材料层的区域中。 还公开了包括包括包括微处理器的封装的计算装置的方法和装置。

公开(公告)号：WO2015047257A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/061762

申请日：2013-09-25

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  IBRAHIM, Tarek A. ,  HANEY, Sarah K. ,  SOBIESKI, Daniel N. ,  ZANTYE, Parshuram B. ,  MAIR, Chad E. ,  KAMGAING, Telesphor

Inventor： TEH, Weng Hong ,  IBRAHIM, Tarek A. ,  SOBIESKI, Daniel N. ,  ZANTYE, Parshuram B. ,  MAIR, Chad E. ,  KAMGAING, Telesphor

IPC: H01L29/84

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C1/00261 ,  B81C1/00277 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/01079

Abstract: Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

Abstract translation: 用于提供半导体封装的精确制造结构的技术和机构。 在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。 种子铜和电镀铜设置在多孔电介质材料层上。 进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。 在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。 氮化硅材料层将绝缘层耦合到另一绝缘层。 每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。

公开(公告)号：WO2013003257A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/043945

申请日：2012-06-25

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  GUZEK, John S.

Inventor： TEH, Weng Hong ,  GUZEK, John S.

CPC classification number: H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

Abstract translation: 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

公开(公告)号：WO2014051817A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/048783

申请日：2013-06-28

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  RAGHUNATHAN, Vinodhkumar

Inventor： TEH, Weng Hong ,  RAGHUNATHAN, Vinodhkumar

IPC: H01L23/64 ,  H01L23/66

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract translation: 描述了包括基板及其制造的电子组件。 一个组件包括嵌入在多层基板中的电介质层中的管芯，以及嵌入多层基板中的介电层中的电介质区域。 多层基板包括裸片侧和接地侧，第一介电区和电介质层延伸到管芯侧。 多个通孔位于第一电介质区域内，通孔延伸到管芯侧的焊盘。 描述和要求保护其他实施例。

公开(公告)号：WO2013074061A1

公开(公告)日：2013-05-23

申请号：PCT/US2011/060522

申请日：2011-11-14

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  ZHONG, Shan

Inventor： TEH, Weng Hong ,  ZHONG, Shan

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0331 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF.A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process.

Abstract translation: 冲模模具背面的过程包括在模具背面薄膜（DBF）中打开凹部以暴露模具中的硅 - 硅通孔（TSV）接触，然后用与TSV触点接触的导电材料填充凹部。 添加的焊料在DBF的水平处耦合到导电材料。随后的管芯在添加的焊料处耦合到第一管芯，以形成由TSV接触，导电材料和添加的焊料组成的电耦合，电 碰撞耦合到随后的模具。 装置和计算机系统使用该过程组装。

公开(公告)号：WO2015047346A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062457

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  HANEY, Sarah K. ,  LIM, Chyi Hwang

Inventor： TEH, Weng Hong ,  HANEY, Sarah K. ,  LIM, Chyi Hwang

IPC: H01L29/84

CPC classification number: B81C1/0015 ,  B81B3/0051 ,  B81B2207/015 ,  B81C1/00476 ,  B81C2203/0714 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/73267

Abstract: A semiconductor package comprising a suspended beam portion including an arrangement of through-hole structures. In an embodiment, a first surface of the suspended beam portion includes edges each defining in part a respective through-hole of a plurality of through-holes extending between the first surface and a second surface. The first surface comprises a plurality of arm portions each located between a respective pair of edge-adjacent edges. The first surface comprises a plurality of node portions each located at a respective junction of three or more of the plurality of arm portions. In another embodiment, for each of the plurality of node portions, a respective total number of arm portions which join one another at the node portion is a number other than four, or two arm portions which join one another at the node portion have respective mid-lines which are oblique to one another.

Abstract translation: 一种半导体封装，包括包括通孔结构的布置的悬挂梁部分。 在一个实施例中，悬挂梁部分的第一表面包括边缘，每个边缘部分地限定在第一表面和第二表面之间延伸的多个通孔的相应通孔。 第一表面包括多个臂部分，每个臂部分位于相应的一对边缘相邻边缘之间。 第一表面包括多个节点部分，每个节点部分位于多个臂部分中的三个或更多个的相应接合处。 在另一个实施例中，对于多个节点部分中的每个节点部分，在节点部分处彼此连接的臂部分的相应总数是除四个之外的数量，或者在节点部分处彼此连接的两个臂部分分别具有中间 相互倾斜的线条

公开(公告)号：WO2015047324A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062349

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  OSTER, Sasha ,  HANEY, Sarah ,  TEH, Weng Hong ,  EID, Feras

Inventor： OSTER, Sasha ,  HANEY, Sarah ,  TEH, Weng Hong ,  EID, Feras

IPC: H01L23/552

CPC classification number: H05K9/0052 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/243 ,  B32B2457/00 ,  B81B7/0029 ,  B81B7/0032 ,  B81B7/02 ,  B81C1/0023 ,  G06F1/182 ,  H01L21/568 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H05K1/115 ,  Y10T156/10 ,  H01L2924/00

Abstract: Magnetic field shielding material with high relative permeability incorporated into a build-up package, for example to restrict a field of a magnet integrated with the build-up to a target device configured to operate in the field. In embodiments, a first device is physically coupled to the build-up. In embodiments, a magnetic field shielding material is disposed in contact with the build-up and in proximity to the first device to restrict a magnetic field either to a region occupied by the first device or to a region exclusive of the first device. A field shielding material may be disposed within build-up near a permanent magnet also within the build-up to reduce exposure of another device, such as an IC, to the magnetic field without reducing MEMS device exposure.

Abstract translation: 具有高的相对磁导率的磁场屏蔽材料被并入到积聚封装中，例如将与积聚物集成的磁体的场限制到被配置为在现场操作的目标装置。 在实施例中，第一设备物理地耦合到建立。 在实施例中，磁场屏蔽材料设置成与积层接触并且靠近第一装置，以将磁场限制到由第一装置占据的区域或不包括第一装置的区域。 场屏蔽材料也可以在堆积物内的永磁体附近的堆积内设置，以减少诸如IC之类的其它器件（例如IC）的暴露，而不会降低MEMS器件的暴露。

公开(公告)号：WO2013066294A1

公开(公告)日：2013-05-10

申请号：PCT/US2011/058598

申请日：2011-10-31

Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  GUZEK, John S. ,  ZHONG, Shan

Inventor： TEH, Weng Hong ,  GUZEK, John S. ,  ZHONG, Shan

IPC: H01L23/12 ,  H01L25/18 ,  H01L23/16

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi chip modules), systems on chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic to memory, memory to memory, and logic to logic interface stacking assemblies.

Abstract translation: 描述了封装集成电路和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建筑结构，其可以例如三维（3D）封装（或封装（SiP）或多芯片模块中的系统），片上3D封装以及混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器以及逻辑到逻辑接口堆叠组件。