公开(公告)号：EP1394856A3

公开(公告)日：2005-08-31

申请号：EP03255207.7

申请日：2003-08-22

申请人： Fujitsu Media Devices Limited

发明人： Furukawa, Osamu ,  Murata, Toshihiko ,  Ikata, Osamu

IPC分类号： H01L25/065 ,  H03H9/05

CPC分类号： H01L25/50 ,  H01L24/45 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/165 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A surface-mounted electronic component module includes a wiring substrate (1) having wiring patterns (2) formed on one side and external connection terminals (3) formed on the other side, the wiring patterns and the external connection terminals being connected with each other by via holes or through holes; a plurality of electronic component devices (4, 7) mounted on the one side of the wiring substrate (1); and an exterior resin layer (16) formed on the wiring substrate which covers the plurality of electronic component devices (4, 7), wherein at least one of the plurality of electronic component devices is fastened face up on the one side of the wiring substrate (1), the connection terminal (6) of the electronic component device (4, 7) fastened face up and the wiring pattern (2) or the connection terminal (6) of another electronic component device being connected with each other by wire (15).

摘要翻译： 表面安装的电子部件模块包括具有形成在一侧的布线图案（2）和形成在另一侧的外部连接端子（3）的布线基板（1），布线图案和外部连接端子彼此连接 通孔或通孔; 安装在所述布线基板（1）一侧的多个电子部件装置（4,7）; 以及形成在所述布线基板上的覆盖所述多个电子部件装置（4,7）的外部树脂层（16），其中，所述多个电子部件装置中的至少一个被正面朝上地紧固在所述布线基板的一侧 （1）中，电子部件装置（4,7）的连接端子（6）正面朝上固定，并且另一个电子部件装置的布线图案（2）或连接端子（6）通过导线（ 15）。

公开(公告)号：EP1543556A2

公开(公告)日：2005-06-22

申请号：EP03748499.5

申请日：2003-09-22

申请人： Advanced Interconnect Technologies Limited

发明人： ISLAM, Shafidul ,  SAN ANTONIO, Romarico, Santos ,  GULTOM, Lenny, Christina

IPC分类号： H01L23/31 ,  H01L21/68 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4985 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a taped lead frame for use in manufacturing electronic packages. The taped lead frame is composed of a tape and a lead frame formed from a plurality of individual metal features attached to the tape and arranged in a footprint pattern. The method of making the invention enables the thickness of conventional frames to shrink significantly to result in thinner packages for improved heat dissipation and shorter geometries for improved electrical performance. A plurality of such lead frames are arranged in an array on a sheet of tape and each lead frame is separated from surrounding lead frames by street regions on the tape such that no metal feature extends into a street region. Integrated circuit chips are attached and electrically connected to the lead frames and an encapsulant is applied, cured and dried over the lead frames and the street regions. Thereafter, the tape is removed and the lead frames are singulated by cutting through the encapsulant in the street regions to form individual packages. Singulation occurs in the street regions and does not cut into any metal feature forming the lead frame.

公开(公告)号：EP1213754A3

公开(公告)日：2005-05-25

申请号：EP02003791.7

申请日：1995-03-17

申请人： HITACHI CHEMICAL CO., LTD.

发明人： Fukutomi, Naoki ,  Tsubomatsu, Yoshiaki ,  Inoue, Fumio ,  Yamazahki, Toshio ,  Ohhata, Hirohito ,  Hagiwara, Shinsuke ,  Taguchi, Noriyuki ,  Nomura, Hiroshi

IPC分类号： H01L21/68 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0002

摘要： A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

摘要翻译： 提供了半导体封装基板，可以满足向半导体集成度高的趋势。 将镍层电镀在电镀铜箔上以形成布线图案。 将LSI芯片安装在铜箔上，通过引线接合连接LSI芯片和布线图案的端子，然后用半导体密封型环氧树脂密封。 只有铜箔用碱蚀刻剂溶解掉才能暴露镍。 对于具有低铜溶力的镍剥离器，去除镍层以露出布线图案。 涂覆阻焊剂，并且以使得连接端子部分露出的方式形成图案。 将焊球放置在布线图案的露出部分，然后熔合。 布线图案通过焊球与外部印刷电路板连接。

公开(公告)号：EP1527480A2

公开(公告)日：2005-05-04

申请号：EP03784529.4

申请日：2003-08-05

申请人： Casio Computer Co., Ltd.

发明人： JOBETTO, Hiroyasu ,  MIHARA, Ichiro

IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L23/31

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor construction assembly (23) having a semiconductor substrate (24) which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads (25) which are connected to the integrated circuit element, a protective layer (27) which covers the semiconductor substrate and has openings (28) for exposing the connection pads (25), and conductors (31) which are connected to the connection pads (25), arranged on the protective layer (27), and have pads. An upper insulating layer (37) covers the entire upper surface of the semiconductor construction assembly (23) including the conductors (31) except the pads. A sealing member (34 or 36) covers at least one side surface of the semiconductor construction assembly (23). An upper conductors (43) is formed on the upper insulating layer, and has one ends electrically connected to the pads and an external connection pads, respectively, an external connection pad of at least one of the upper conductors being disposed in a region corresponding to the sealing member.

摘要翻译： 一种半导体器件，包括：具有半导体衬底（24）的半导体构造组件（23），所述半导体衬底具有第一和第二表面并具有形成在所述第一表面上的集成电路元件;多个连接焊盘（25） 集成电路元件，覆盖半导体衬底并具有用于暴露连接焊盘（25）的开口（28）的保护层（27），以及连接到连接焊盘（25）的导体（31），布置在保护层 层（27），并具有垫。 上绝缘层（37）覆盖半导体构造组件（23）的整个上表面，除了焊盘之外，包括导体（31）。 密封构件（34或36）覆盖半导体构造组件（23）的至少一个侧表面。 上导体（43）形成在上绝缘层上，并且其一端分别电连接到焊盘和外连接焊盘，至少一个上导体的外连接焊盘设置在对应于 密封构件。

公开(公告)号：EP1517371A2

公开(公告)日：2005-03-23

申请号：EP04030843.9

申请日：1997-03-06

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Takata, Hirofumi ,  Tanida, Tadashi

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K3/3426 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of fabricating a plurality of electronic components of a resin molded package type, said method comprising: over a plate-like lead frame comprising a plurality of bridge parts which are formed into a lattice and a plurality of sets of lead parts which extend towards a plurality of lattice open spaces which are horizontally and perpendicularly, and two-dimensionally defined by said plurality of bridge parts, a step of fixing each of a plurality of electronic elements in a corresponding lattice open space of said plurality of lattice open spaces.

摘要翻译： 一种制造树脂密封封装型的电子组件的多个方法，所述方法包括：在板状的引线框架，其包括连接部分的多个形成为格子和的组引线部的多个朝向延伸 栅格空间哪些是水平地和垂直地，和二维地通过的桥部分，所述多个，在所述多个栅格空间中的对应的格子的开放空间的每个电子元件的多个固定的步骤中定义的复数。

公开(公告)号：EP1487014A1

公开(公告)日：2004-12-15

申请号：EP03746477.3

申请日：2003-04-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： SAKAI, Tadahiko ,  OZONO, Mitsuru ,  WADA, Yoshiyuki

IPC分类号： H01L23/12

CPC分类号： H01L24/27 ,  H01L23/12 ,  H01L23/3114 ,  H01L24/29 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/01082 ,  Y10S438/959 ,  H01L2224/83 ,  H01L2924/3512 ,  H01L2924/00

摘要： In a semiconductor device provided with a thinned semiconductor element, the present invention intends to provide a semiconductor device in which a damage of a semiconductor element is inhibited from occurring in the neighborhood of an outer periphery and thereby the reliability can be secured. In order to realize the object, the invention relates to a semiconductor device in which to a rear surface of a thinned semiconductor element on a front surface of which a plurality of external connection terminals is formed, a plate higher in the rigidity than the semiconductor element is adhered with a resin binder, wherein an outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.

摘要翻译： 在具有减薄的半导体元件的半导体器件中，本发明旨在提供一种半导体器件，其中半导体元件的损伤被抑制在外周附近，从而可以确保可靠性。 为了实现该目的，本发明涉及一种半导体器件，其中在形成有多个外部连接端子的前表面上的薄型半导体元件的后表面上，刚性比半导体元件高的板 粘附有树脂粘合剂，其中板的外部形状比半导体元件的外形大，并且树脂粘合剂覆盖半导体元件的侧面，以形成用于加强半导体元件的周边的加强部分。

公开(公告)号：EP1456880A2

公开(公告)日：2004-09-15

申请号：EP02791626.1

申请日：2002-12-11

申请人： Infineon Technologies AG

发明人： REISS, Martin

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to an electronic component (1) and a method for producing the same. Said electronic component (1) comprises a semiconductor chip (2), a rewiring plate (3) and a plastic housing (4) which is divided into two plastic parts (23) arranged one on top of the other. A first layer (5) forming one of the plastic housing parts (23) has a relatively uneven surface which is smoothed by a second layer (6) forming the other plastic housing part (23), in such a way that the electronic component (1) is provided with a plastic housing (4) having smooth outer sides.

公开(公告)号：EP1394856A2

公开(公告)日：2004-03-03

申请号：EP03255207.7

申请日：2003-08-22

申请人： Fujitsu Media Devices Limited

发明人： Furukawa, Osamu ,  Murata, Toshihiko ,  Ikata, Osamu

IPC分类号： H01L25/065

CPC分类号： H01L25/50 ,  H01L24/45 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/165 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A surface-mounted electronic component module includes a wiring substrate (1) having wiring patterns (2) formed on one side and external connection terminals (3) formed on the other side, the wiring patterns and the external connection terminals being connected with each other by via holes or through holes; a plurality of electronic component devices (4, 7) mounted on the one side of the wiring substrate (1); and an exterior resin layer (16) formed on the wiring substrate which covers the plurality of electronic component devices (4, 7), wherein at least one of the plurality of electronic component devices is fastened face up on the one side of the wiring substrate (1), the connection terminal (6) of the electronic component device (4, 7) fastened face up and the wiring pattern (2) or the connection terminal (6) of another electronic component device being connected with each other by wire (15).

公开(公告)号：EP1045443A3

公开(公告)日：2004-01-21

申请号：EP00301638.3

申请日：2000-03-01

申请人： SHARP KABUSHIKI KAISHA

发明人： Dotta, Yoshihisa ,  Saza, Yasuyuki ,  Tamaki, Kazuo

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/85399 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19043 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/92247 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： When a first semiconductor chip is installed on a circuit substrate by using an anisotropic conductive bonding agent, one portion thereof is allowed to protrude outside the first semiconductor chip. A second semiconductor chip is installed on the first semiconductor chip and a support portion formed by the protruding resin. The protruding portion of the second semiconductor chip is supported by the support portion from under. Thus, in a semiconductor device having a plurality of laminated semiconductor chips in an attempt to achieve a high density, even when, from a semiconductor chip stacked on a circuit substrate, one portion of a semiconductor chip stacked thereon protrudes, it is possible to carry out a better wire bonding process on electrodes formed on the protruding portion.

摘要翻译： 当通过使用各向异性导电粘合剂将第一半导体芯片安装在电路基板上时，允许其一部分突出到第一半导体芯片的外部。 第二半导体芯片安装在第一半导体芯片上以及由突出树脂形成的支撑部分。 第二半导体芯片的突出部分从底部由支撑部分支撑。 因此，为了实现高密度化，在具有多层叠半导体芯片的半导体装置中，即使从堆积在电路基板上的半导体芯片的一部分堆叠的半导体芯片突出，也可以携带 在形成在突出部分上的电极上形成更好的引线接合工艺。

公开(公告)号：EP1359612A2

公开(公告)日：2003-11-05

申请号：EP03009358.7

申请日：2003-04-24

申请人： Sanyo Electric Co., Ltd.

发明人： Mizutani, Masahiko ,  Takakusaki, Sadamichi ,  Nezu, Motoichi ,  Motegi, Kazutoshi ,  Noguchi, Mitsuru

IPC分类号： H01L21/304

CPC分类号： H01L21/481 ,  H01L21/4878 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19105 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09745 ,  H05K2203/0228 ,  H05K2203/1572 ,  H05K2203/302 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00

摘要： In preferred embodiments, a method of manufacturing a hybrid integrated circuit device is provided, in which a plurality of circuit substrates (10) are manufactured from a single metal substrate (10A') by dicing. In some embodiments, the method includes: preparing a metal substrate (10A') having an insulating layer (11) formed on the top surface thereof; forming a plurality of conductive patterns (12) on the top surface of insulating layer (11); forming grooves (20) in lattice form on the rear surface of metal substrate (10B'); mounting hybrid integrated circuits onto conductive patterns (12); and separating individual circuit substrates (10) with, for example, a rotatable cutter.

摘要翻译： 在优选实施例中，提供了一种制造混合集成电路器件的方法，其中通过切割由单个金属衬底（10A'）制造多个电路衬底（10）。 在一些实施例中，该方法包括：制备在其顶表面上形成有绝缘层（11）的金属衬底（10A'）; 在绝缘层（11）的顶表面上形成多个导电图案（12）; 在金属基板（10B'）的后表面上形成格子状的槽（20）; 将混合集成电路安装到导电图案（12）上; 以及用例如可旋转切割器分离各个电路基板（10）。