公开(公告)号：EP2037722A2

公开(公告)日：2009-03-18

申请号：EP08006205.2

申请日：2008-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kim, Kwan-Ho ,  Jang, Ick-Kyu ,  Myeong, Ji-Man

IPC: H05K1/00

CPC classification number: H05K1/0219 ,  G09G3/3696 ,  G09G2330/06 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: A printed circuit board ("PCB") includes a first pattern structure, a second pattern structure, a third pattern structure, and a fourth pattern structure. The first pattern structure includes a first ground pattern. The second pattern structure includes a first line pattern overlapping the first ground pattern and a second ground pattern electrically insulated from the first line pattern. The third pattern structure includes a third ground pattern overlapping the first line pattern and a second line pattern overlapping the second ground pattern. The fourth pattern structure includes a fourth ground pattern overlapping the second line pattern. Therefore, the PCB may decrease noise.

Abstract translation: 一种印刷电路板（“PCB”）包括第一图样结构，第二图样结构，第三图样结构，以及第四图样结构。 第一图样结构包括第一接地图案​​。 该第二图样结构包括第一线条图样重叠第一接地图案​​和从第一线条图样电绝缘的第二底样。 该第三图样结构包括第三接地图案的第一线条图样和第二线图案重叠第二接地图案交叠。 该第四图样结构包括第四底样的第二线条图样重叠。 因此，PCB可以减少噪音。

公开(公告)号：EP2031944A1

公开(公告)日：2009-03-04

申请号：EP08704242.0

申请日：2008-01-31

Applicant: Nippon Mektron, Limited

Inventor： TOYOSHIMA, Ryoichi

IPC: H05K1/02

CPC classification number: H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/09236 ,  H05K2201/09272

Abstract: The present invention provides a microstrip line for a printed wiring board such as a flexible printed wiring board which includes a sandwiched thin insulating layer and cannot use a solid grounding conductor, the microstrip line being such that shape of grounding conductors relative to signal lines remains unchanged even in the presence of a curved shape and that overlapping areas of signal lines and grounding conductors located opposite to each other remain unchanged even in case of exposure misalignment or stack misalignment. A printed wiring board with a microstrip line structure in which signal lines are curved include wire-type grounding conductors 5, 9, 12, 15, 19, or 26 located across an insulating layer 3, 10, or 13 from the signal lines 4, 6, 8, 11, 14, 18, or 25, characterized in that wiring pitch of the grounding conductors is 1/n of width of the signal lines (where n is a natural number of 1 or 2).

Abstract translation: 本发明提供一种用于诸如柔性印刷线路板的印刷线路板的微带线，该柔性印刷线路板包括夹在中间的薄绝缘层并且不能使用固体接地导体，该微带线使得相对于信号线的接地导体的形状保持不变 即使在存在弯曲的形状的情况下，即使在曝光未对准或堆叠未对准的情况下，彼此相对的信号线和接地导体的重叠区域也保持不变。 具有其中信号线弯曲的微带线结构的印刷线路板包括位于与信号线4隔开的绝缘层3,10或13上的线型接地导体5,9,12,15,19或26， 其特征在于接地导体的布线间距是信号线宽度的1 / n（其中n是1或2的自然数）。

公开(公告)号：EP2022143A1

公开(公告)日：2009-02-11

申请号：EP07775102.2

申请日：2007-04-10

Applicant: ADC Telecommunications, Inc.

Inventor： HAMMOND, JR., Bernard ,  MURRAY, David P. ,  GEORGE, Ian R.

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/6658 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes first and second conductive layers separated by a relatively thin dielectric layer. The first and second conductive layers include a crosstalk compensation arrangement having spaced-apart capacitor members. The relatively thin dielectric layer allows a high level of capacitance to be generated between the capacitor members.

公开(公告)号：EP2008346A2

公开(公告)日：2008-12-31

申请号：EP07775101.4

申请日：2007-04-10

Applicant: ADC Telecommunications, Inc.

Inventor： HAMMOND, JR., Bernard ,  MURRAY, David P. ,  GEORGE, Ian R.

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2429 ,  H01R13/6477 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a crosstalk compensation arrangement for reducing crosstalk at the jack. The circuit board also includes arrangements that reduce return loss at the jack.

公开(公告)号：EP1670300A3

公开(公告)日：2008-12-03

申请号：EP06004650.5

申请日：1999-05-13

Applicant: IBIDEN CO., LTD.

Inventor： Hirose, Naohiro, c/o Ogaki-kita-kojou ,  Mori, Yoji, c/o Ogaki-kita-kojou ,  Kariya, Takashi, c/o Ogaki-kita-kojou

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed wiring board having a conductor portion and a wiring pattern, wherein a narrow width portion is formed in the wiring pattern in accordance with a distance from an adjacent conductor portion.

公开(公告)号：EP1935634A1

公开(公告)日：2008-06-25

申请号：EP06026416.5

申请日：2006-12-20

Applicant: Scheuten S.à.r.l.

Inventor： Rothfusz, Paul

IPC: B32B17/10 ,  H05B3/84 ,  H05K3/20

CPC classification number: H05K1/0296 ,  B32B17/10 ,  B32B17/10036 ,  B32B17/10174 ,  B32B17/10247 ,  B32B17/10376 ,  B32B17/10761 ,  H01Q1/1278 ,  H05B3/84 ,  H05B2203/002 ,  H05B2203/017 ,  H05K2201/09236 ,  H05K2201/09263 ,  B32B2367/00

Abstract: The present invention concerns a method for randomly patterning electrically conductive elements (6), the patterned electrically conductive elements produced thereby and their use for example as heating elements or antennas.

Abstract translation: 本发明涉及一种用于随机图案化的导电元件（6），由此产生的图案化的导电元件及对实施例作为加热元件或天线使用的方法。

公开(公告)号：EP1300768A3

公开(公告)日：2008-03-26

申请号：EP02256552.7

申请日：2002-09-20

Applicant: SUN MICROSYSTEMS, INC.

Inventor： Williams, Ricki D.

IPC: G06F13/40

CPC classification number: H05K1/025 ,  H04L49/101 ,  H04L49/40 ,  H05K1/0245 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09309

Abstract: An apparatus comprises a first plane adapted to receive a first voltage level and a second plane adapted to receive a second voltage level. The apparatus further comprises a path asymmetrically positioned between the first plane and the second plane. The path is capable of providing the network connection to one or more devices within a processor-based system, typically for the purpose of management of one or more domains in the system.

公开(公告)号：EP1349418A3

公开(公告)日：2007-11-21

申请号：EP03251685.8

申请日：2003-03-19

Applicant: Guangdong Telecom Academy of Science & Technology

Inventor： Luo, Senwen ,  Lai, Shineng ,  Zhang, Yinhuan

IPC: H04Q11/04 ,  H02H9/04

CPC classification number: H05K1/0257 ,  H04Q11/04 ,  H04Q2213/13003 ,  H04Q2213/1308 ,  H04Q2213/13166 ,  H04Q2213/13299 ,  H05K1/0259 ,  H05K1/14 ,  H05K1/18 ,  H05K2201/09236

Abstract: The invention discloses a method for overvoltage protection at bus interface of a time switch circuit board in an exchange. The method comprises adding a voltage-limited protection circuit, unidirectional or bidirectional, between every driver/receiver signal line of TS-BUS and the earth. The invention also discloses a device for overvoltage protection according to the method. The device comprises a printed board that has socket connectors on two sides and overvoltage protection circuits on the middle, the overvoltage protection circuits are voltage-limited circuits and each of them is connected between every driver/receiver line of TS-BUS and the earth in a bypass mode.

公开(公告)号：EP1549118A3

公开(公告)日：2007-07-18

申请号：EP04257721.3

申请日：2004-12-13

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Lauffer, John M. ,  Markovich, Voya R. ,  McNamara, James J., Jr. ,  Thomas, David L.

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board (10) and a method of making same in which the board includes a common power plane (11) having dielectric layers (19, 23) on opposing sides thereof and a signal layer (21, 25) on each of said dielectric layers (19, 23), each signal layer comprising a plurality of substantially parallel signal lines (22, 27) running in substantially similar directions across said signal layers (21, 25). Predetermined portions of the signal lines (22, 27) in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane (11) being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes (13) in the power plane (11) so as to be isolated therefrom.

公开(公告)号：EP0924969A3

公开(公告)日：2007-02-21

申请号：EP99104811.7

申请日：1998-01-27

Applicant: LUCENT TECHNOLOGIES INC.

Inventor： Carter, Galen L. ,  Norte, David A. ,  Yoon, Woong K.

IPC: H05K1/02 ,  H03H1/00 ,  H01F17/00 ,  H01F17/04

CPC classification number: H03H1/0007 ,  H01F17/0006 ,  H01F17/06 ,  H01F2017/065 ,  H05K1/0233 ,  H05K1/0237 ,  H05K1/165 ,  H05K1/182 ,  H05K3/222 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09245

Abstract: A printed circuit (PC) board-mountable ferrite electromagnetic interference (EMI) filter (702, 1003, 1003'') for striplines (701, 1001, 1002) of a printed circuit (PC) board (700, 1000) that accommodates large numbers of striplines, and is cost-effective. One embodiment of the EMI filter is used with a PC board (700) that routes striplines (701) in a step-function (i.e., a "U"-shaped) pattern. The EMI filter comprises a ferrite body (702) that defines two parallel passageways (708, 709), i.e., has a figure-8 shape in cross section. The portion (710) of the PC board that defines the stripline portions extending in the one direction lies in one passageway, whereas the portion (711) of the PC board that defines the stripline portions extending in the other direction lies in the other passageway. A different embodiment of the EMI filter is used with a PC board (1000) that routes sets (1001, 1002) of striplines in a cross-hatch (i.e., a "#"-shaped) pattern, where the striplines end (are interrupted) before intersecting so that each stripline comprises two separate straight on-board parts. This EMI filter comprises a ferrite body (1003) that defines two orthogonal sets (1012, 1013) of off-board "U"-shaped conductors, one set for each orthogonal set of striplines with one conductor of a set for each stripline of a set. Each stripline's corresponding "U"-shaped conductor interconnects the two straight on-board parts of the stripline.