公开(公告)号：EP1123988B1

公开(公告)日：2008-07-09

申请号：EP00204364.4

申请日：2000-12-07

Applicant: Nikko Materials USA, Inc.

Inventor： Wang, Jiangtao ,  Callahan, John ,  Lillie, Dan

IPC: C23C14/02 ,  H05K3/14 ,  C23C28/00

CPC classification number: H05K1/167 ,  C23C2/02 ,  C23C2/26 ,  C23C14/024 ,  C23C14/025 ,  C23C28/321 ,  C23C28/322 ,  C23C28/3225 ,  C23C28/345 ,  C23C28/3455 ,  H05K3/384 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T428/12438

公开(公告)号：EP1278404B1

公开(公告)日：2008-03-12

申请号：EP02729553.4

申请日：2002-01-11

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

Inventor： SUGAWA, Toshio ,  MURAKAWA, Satoshi ,  HAYAMA, Masaaki ,  YASUHO, Takeo

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/4069 ,  H05K1/095 ,  H05K2201/0305 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board produced by the step of filling a via hole (102), formed in an insulating substrate (101), with a conductive material (103), the step of providing conductive layers (104) on the opposite surface of the insulating substrate, and the step of alloying the component materials of the conductive material with those of the conductive layer. The conductive material filled in the via hole provided in the insulating substrate and conductive layers on the opposite surfaces of insulating substrate are electrically and mechanically connected together so as to positively ensure a high reliability.

Abstract translation: 通过在导电材料（103）上填充形成在绝缘衬底（101）中的通孔（102）的步骤制造的电路板，在绝缘衬底（101）的相对表面上提供导电层（104） 以及将导电材料的组分材料与导电材料的组分材料合金化的步骤。 填充在设置在绝缘基板中的通孔中的导电材料和绝缘基板的相对表面上的导电层被电连接和机械连接在一起，从而确实确保高可靠性。

公开(公告)号：EP1872941A1

公开(公告)日：2008-01-02

申请号：EP05757943.5

申请日：2005-07-01

Applicant: Toyo Boseki Kabushiki Kaisha

Inventor： MAEDA, Satoshi c/o Toyo Boseki Kabushiki Kaisha ,  KAWAHARA, Keizo c/o Toyo Boseki Kabushiki Kaisha ,  TSUTSUMI, M. c/o Toyo Boseki Kabushiki Kaisha ,  YOSHIDA, Takefumi c/o Toyo Boseki Kabushiki Kaisha

IPC: B32B27/34

CPC classification number: H05K1/0346 ,  H05K3/181 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2203/065 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: The thin film-laminated polyimide film contains a substrate film and a thin film layer formed at least on one surface of the substrate film. The substrate film is made of a polyimide film showing a degree of curl after a heat treatment at 300°C of not more than 10%. Use of this thin film-laminated polyimide film as a substrate of electronic parts such as solar battery, capacitor and the like exposed to high temperatures prevents easy development of warpage and distortion during production, and can improve quality and yield of electronic parts.

Abstract translation: 薄膜叠层聚酰亚胺膜含有基材膜和至少在基材膜的一个表面上形成的薄膜层。 基材膜由聚酰亚胺膜制成，其在300℃下热处理后的卷曲度不大于10％。 使用这种薄膜叠层的聚酰亚胺膜作为暴露于高温的太阳能电池，电容器等电子部件的基板，防止了在生产过程中容易发生翘曲和变形，并且可以提高电子部件的质量和产量。

公开(公告)号：EP1211730B1

公开(公告)日：2008-01-02

申请号：EP01309248.1

申请日：2001-10-31

Applicant: Nokia Corporation

Inventor： Pohjonen, Helena

IPC: H01L25/16 ,  H01L23/367 ,  H05K1/02

CPC classification number: H05K1/0207 ,  H01L23/3677 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/141 ,  H05K1/16 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0317 ,  H05K2201/09563 ,  H01L2924/00

公开(公告)号：EP1843648A2

公开(公告)日：2007-10-10

申请号：EP07104107.3

申请日：2007-03-14

Applicant: Nitto Denko Corporation

Inventor： Ishii, Jun ,  Ooyabu, Yasunari

IPC: H05K1/02

CPC classification number: H05K1/0259 ,  H05K1/056 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2203/0315

Abstract: A wired circuit board includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, a first semi-conductive layer formed on the conductive pattern, an insulating cover layer formed on the first semi-conductive layer, and a second semi-conductive layer formed on the insulating cover layer. The first semi-conductive layer and the second semi-conductive layer are electrically connected to the metal supporting board.

Abstract translation: 布线电路板包括金属支撑板，形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，形成在导电图案上的第一半导电层，形成在金属支撑板上的绝缘覆盖层 第一半导体层和形成在绝缘覆盖层上的第二半导体层。 第一半导体层和第二半导电层电连接到金属支撑板。

公开(公告)号：EP1697102A2

公开(公告)日：2006-09-06

申请号：EP04784783.5

申请日：2004-09-16

Applicant: Sipix Imaging, Inc.

Inventor： CHAUG, Yi-Shung ,  WANG, Xiaojia ,  KILUK, Sean ,  TSENG, Scott ,  ZANG, HongMei ,  LIANG, Rong-Chang

IPC: B29C31/00

CPC classification number: H05K3/048 ,  B29C45/14811 ,  B29K2995/002 ,  B32B38/10 ,  C23C14/042 ,  C23C14/086 ,  C23C14/20 ,  G02F1/13439 ,  G09F7/165 ,  H01L51/0022 ,  H05K3/04 ,  H05K3/146 ,  H05K3/16 ,  H05K3/184 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2203/0257 ,  H05K2203/0264 ,  H05K2203/0522 ,  H05K2203/0746 ,  Y10S156/922 ,  Y10T156/11 ,  Y10T156/1189

Abstract: A process for forming a patterned thin film structure on a substrate or in-mold decoration film is disclosed. A pattern (204, 504, 506) is printed with a material, such as a masking coating or ink, on the substrate (202, 502), the pattern (204, 504, 506) being such that, in one embodiment, the desired structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern (204, 504, 506) is printed with a material that is difficult to strip from the substrate (202, 502), and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material (206, 508) is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structure.

公开(公告)号：EP1082882A4

公开(公告)日：2005-10-12

申请号：EP00923062

申请日：2000-01-18

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  ZHANG MIN-XIAN ,  SAVIC JOHN

IPC: H01C1/032 ,  H01C7/00 ,  H01C17/06 ,  H05K1/09 ,  H05K1/16 ,  H05K3/38 ,  H01L21/302

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/0723 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/4913

Abstract: Printed circuit boards (6) with integral high and low value resistors (2 and 4) are efficiently produced. The method of their manufacture entails applying a first layer of a low resistance material (8) onto a dielectric substrate (6) in a predetermined thickness and pattern. The pattern defines the electrical lengths and widths of low value resistors (2), as well as pairs of terminal electrode pads (28 and 30) for the high value resistors (4). A second layer of a high resistance material (18) is applied between and in contact with the top surfaces of the facing ends of each member of the terminal pad pairs (28 and 30). The fixed lengths, widths and thicknesses of the patterned high resistance material determine the values of the high value resistors. Conductive metal terminals are provided at the ends of the low value resistors and at the distal ends of the high value resistor pad to complete the resistors.

公开(公告)号：EP1435658A1

公开(公告)日：2004-07-07

申请号：EP02779905.5

申请日：2002-10-07

Applicant: TOKUYAMA CORPORATION

Inventor： YAMAMOTO, Reo ,  KAMIYAMA, Yoshihide

IPC: H01L23/12

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/114 ,  H05K3/0008 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/246 ,  H05K3/4061 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2201/10674 ,  H05K2203/167 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: It is an object to provide a method of efficiently manufacturing a double-sided circuit board having a metallic via hole which can suitably be used as a submount for mounting a semiconductor device, that is, a substrate in which the electrical contact of a metallic via hole and a circuit pattern is excellent and an element can easily be bonded and positioned. In a ceramic substrate having a via hole filled with a conductive material, a ceramic portion of at least one of faces of the ceramic substrate has a surface roughness of Ra ≤ 0.8µm, a substrate in which the conductive material filled in the via hole present on at least one of the faces is protruded from a surface of the face with a height of 0.3 to 5.0µm is used as a material substrate and a conductive layer is formed on the surface, and subsequently, the conductive layer is patterned and a solder film pattern for element mounting is formed based on a position of a convex portion of the conductive layer which results from the via hole present on an underlaid portion of the conductive layer.

Abstract translation: 本发明的目的是提供一种有效地制造具有金属通孔的双面电路板的方法，该金属通孔适合用作用于安装半导体器件的基座，即，金属通孔 孔和电路图案是优异的，元件可以容易地粘合和定位。 在具有填充有导电材料的通路孔的陶瓷基板中，陶瓷基板的表面的至少一面的陶瓷部分的表面粗糙度Ra≤0.8μm，其中导电材料填充在通孔中的基板 存在于至少一个面上的表面的表面以0.3〜5.0μm的高度作为材料基板使用，并且在表面上形成导电层，接着，对导电层进行图案化， 基于存在于导电层的底层部分上的通孔产生的导电层的凸部的位置形成用于元件安装的焊料膜图案。

公开(公告)号：EP1005260A3

公开(公告)日：2004-04-07

申请号：EP99309146.1

申请日：1999-11-17

Applicant: MicroCoating Technologies, Inc.

Inventor： Hunt, Andrew Tye ,  Flanagan, John Scott ,  Neuman, George Andrew

IPC: H05K1/16 ,  H01G4/10 ,  H01G4/08 ,  C23C16/453

CPC classification number: H05K1/162 ,  H01G4/085 ,  H05K3/388 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309

Abstract: Thin layer capacitors are formed from a first flexible metal layer (402,502), a dielectric layer (404,504) between about 0.03 and about 2 microns deposited thereon, and a second flexible metal layer (406,506) deposited on the dielectric layer (404,504). The first flexible metal layer may either be a metal foil (402), such as a copper, aluminum, or nickel foil, or a metal layer (502) deposited on a polymeric support sheet (501). Depositions of the layers is by or is facilitate by combustion chemical vapor deposition or controlled atmosphere chemical vapor deposition.

公开(公告)号：EP1332653A1

公开(公告)日：2003-08-06

申请号：EP01979868.5

申请日：2001-10-17

Applicant: Oak-Mitsui, Inc.

Inventor： ANDRESAKIS, John, A.

IPC: H05K3/06 ,  H05K3/24 ,  H05K3/38

CPC classification number: H05K3/244 ,  H05K3/064 ,  H05K3/384 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/072 ,  H05K2203/0723

Abstract: The invention relates to the manufacture of printed circuit boards having enhanced etch uniformity and resolution. The process eliminates the need for a black oxide treatment to improve adhesion and improves the ability to optically inspect the printed circuit boards. The process is performed by conducting steps (a) and (b) in either order: a) depositing a first surface of an electrically conductive layer onto a substrate, which electrically conductive layer has a roughened second surface opposite to the first surface; b) depositing a thin metal layer onto the roughened second surface of the electrically conductive layer, which metal layer comprises a material having a different etch resistance property than that of the electrically conductive layer. Thereafter one deposits a photoresist onto the metal layer; imagewise exposes and develops the photoresist, thereby revealing underlying portions of the metal layer. The one removes the revealed underlying portions of the metal layer, thereby revealing underlying portions of the conductive layer and removes the revealed underlying portions of the conductive layer, to thereby produce a printed circuit layer.