公开(公告)号：EP1317168A1

公开(公告)日：2003-06-04

申请号：EP01403063.9

申请日：2001-11-29

Applicant: Thomson Licensing S.A.

Inventor： Li, Hua ,  Chin, Yuan Fuat

IPC: H05K1/00

CPC classification number: H05K1/181 ,  H05K2201/09236 ,  H05K2201/09772 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A data bus of a DVD+RW recorder between a DSP and a SDRAM usually needs a multilayer wiring board. In order to simplify the layout of the wiring board of the data bus there is provided a method for connecting at least a first and a second integrated circuit by providing the first integrated circuit having a plurality of first logical I/O ports physically arranged in a first order at the periphery, and providing the second integrated circuit having a plurality of second logical I/O ports physically arranged in a second order at the periphery, wherein each first I/O port is to be connected to one of said second I/O ports. The first and second I/O logical ports are connected independently from the first and/or second physical order, so that connection lines do not cross each other.

Abstract translation: DSP与SDRAM之间的DVD + RW刻录机的数据总线通常需要多层布线板。 为了简化数据总线的布线板的布局，提供了一种通过提供具有物理地布置在第一和第二集成电路中的多个第一逻辑I / O端口的第一集成电路来连接至少第一和第二集成电路的方法 并且提供第二集成电路，该第二集成电路具有多个第二逻辑I / O端口，该第二逻辑I / O端口在外围以二级物理排列，其中每个第一I / O端口将被连接到所述第二I / O端口 第一和第二I / O逻辑端口独立于第一和/或第二物理顺序连接，使得连接线不互相交叉。

公开(公告)号：EP1141887A1

公开(公告)日：2001-10-10

申请号：EP99973502.0

申请日：1999-11-29

Applicant: Gemplus

Inventor： ODDOU, Laurent ,  AYALA, Stéphane ,  ZAFRANY, Micha[l

IPC: G06K19/077

CPC classification number: G06K19/0775 ,  G06K19/07749 ,  H01L24/24 ,  H01L2224/83192 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/284 ,  H05K3/305 ,  H05K2201/09772 ,  H05K2201/10727 ,  Y02P70/613 ,  Y10S257/922 ,  H01L2924/00

Abstract: The invention concerns a method for making a contactless chip card comprising an electronic module (600), and connected to said module, an antenna (200). The inventive method comprises the following steps: producing, on a first support sheet (100), the antenna (200) provided at its ends, with connection terminals (250); producing an insulating bridge (300) partly covering the antenna (200) coils except for the connection terminals (250); depositing a drop of filling material (500) on the insulating bridge; transferring the electronic module (600), its connection pads (610) being oriented towards the insulating bridge (300); then providing an electric connection between the module (600) contact pads and the antenna (200) connection terminals (250).

公开(公告)号：EP0995346A1

公开(公告)日：2000-04-26

申请号：EP99922215.1

申请日：1999-05-04

Applicant: Nokia Networks Oy

Inventor： ISOKOSKI, Arto ,  MARJAKANGAS, Jari

IPC: H05K7/20

CPC classification number: H05K1/0212 ,  H01L23/345 ,  H01L2924/0002 ,  H05K3/3494 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/09645 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: The present invention relates to a heating method and a printed circuit board comprising a heating element (90) which generates heat required to heat printed circuit board components. The printed circuit board comprises heat conductor (40) between the heating element (90) and the component to be heated, the heat conductor receiving heat generated by the heating element (90) and conducting the heat along the surface of the printed circuit board beneath the lower surface of the component to be heated. Furthermore, the printed circuit board comprises conductor parts (15, 70) which are narrower than the heat conductor (40), or which have a smaller cross-sectional surface area than does the heat conductor, and which restrict heat transfer away from the heat conductor (40) to a component other than the one to be heated when the heat conductor (40) functions as a ground plane or a signal path.

公开(公告)号：EP0970522A1

公开(公告)日：2000-01-12

申请号：EP98964132.9

申请日：1998-12-18

Applicant: MOLEX INCORPORATED

Inventor： NODA, Atsuhito ,  OKANO, Masato ,  FUJII, Hiroyuki

IPC: H01L23/498 ,  H05K3/34

CPC classification number: H05K1/0212 ,  G01R1/07307 ,  G01R31/2886 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/167 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/049 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/09772 ,  H05K2201/10378 ,  H05K2203/1115 ,  H05K2203/162 ,  Y02P70/613

Abstract: An improved connector assembly (1) particularly useful for testing semiconductor devices of ball grid array ('BGA') structure (10) with a plurality of solder balls (11) formed on the surface thereof. The balls (11) are placed into contact with opposing conductive portions (3a) of the connector assembly. A heat generating member (7), such as a wire, is disposed proximate to the connector assembly conductive portions (3a) and may be selectively energized to generate heat to partially melt the solder balls (11). Reliable connections are effected in this manner.

公开(公告)号：EP0926930A2

公开(公告)日：1999-06-30

申请号：EP98309866.6

申请日：1998-12-02

Applicant: Hewlett-Packard Company

Inventor： Wharton, Robert J. ,  Daniel, Eric R. ,  Brown, Joseph D.

IPC: H05K1/11 ,  H05K1/02 ,  H05K13/08 ,  G01R31/28

CPC classification number: G01R31/316 ,  H05K1/0268 ,  H05K1/111 ,  H05K3/3436 ,  H05K13/08 ,  H05K2201/0761 ,  H05K2201/09345 ,  H05K2201/09772 ,  H05K2201/10106 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A printed circuit board (10) has a first image (11). In the first image (11) there is a first ball grid array pattern (61) for attaching a first input/output ball grid array package. The first ball grid array pattern (61) includes a de-populated center area. A first surface insulation resistance pattern (62) is laid out within the de-populated center area of the first ball grid array pattern (61). A second ball grid array pattern (24) also may be contained within the first image (11). The second ball grid array pattern (24) is for attaching a second input/output ball grid array package. The second ball grid array pattern (24) has rows of interconnect pads (81). A second surface insulation resistance pattern (82) is laid out between the rows of interconnect pads (81).

Abstract translation: 印刷电路板（10）具有第一图像（11）。 在第一图像（11）中，存在用于附接第一输入/输出球栅阵列封装的第一球栅阵列图案（61）。 第一球栅阵列图案（61）包括去填充的中心区域。 第一表面绝缘电阻图案（62）布置在第一球栅阵列图案（61）的去填充的中心区域内。 第二球栅阵列图案（24）也可以包含在第一图像（11）内。 第二球栅阵列图案（24）用于附接第二输入/输出球栅阵列封装。 第二球栅阵列图案（24）具有一排互连焊盘（81）。 第二表面绝缘电阻图案（82）布置在互连焊盘（81）的行之间。

公开(公告)号：EP0766503A3

公开(公告)日：1999-03-31

申请号：EP96115548.8

申请日：1996-09-27

Applicant: CANON KABUSHIKI KAISHA

Inventor： Ohtaki, Toru, c/o Canon K.K. ,  Ichida, Yasuteru, c/o Canon K.K. ,  Takeuchi, Yasushi, c/o Canon K.K.

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H01L23/48 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3421 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.

Abstract translation: 在其上安装有多个电源引脚和多个信号引脚的LSI的多层印刷电路板和采用该印刷电路板的栅格阵列封装中，多个电源引脚中的一些或全部 通过电感图案连接到电源图案，从而减少辐射噪声的产生。

公开(公告)号：EP0817266A3

公开(公告)日：1998-11-25

申请号：EP97110666.1

申请日：1997-06-30

Applicant: NEC Corporation

Inventor： Tanaka, Shinji

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H05K1/0218 ,  H01L23/36 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/32 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K1/0243 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/09772 ,  H05K2201/10666 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/2036

Abstract: A mounting structure for an integrated circuit device comprises a first substrate, a second substrate and an insulator. The first substrate contains conductive wiring electrically connected to the integrated circuit device. The first substrate is mounted on the second substrate which have a ground pattern. The insulator is provided between the conductive wiring and the ground pattern.

Abstract translation: 集成电路器件的安装结构包括第一衬底，第二衬底和绝缘体。 第一基板包含电连接到集成电路器件的导电布线。 第一基板安装在具有接地图案的第二基板上。 绝缘体设置在导电布线和接地图案之间。

公开(公告)号：EP0817266A2

公开(公告)日：1998-01-07

申请号：EP97110666.1

申请日：1997-06-30

Applicant: NEC Corporation

Inventor： Tanaka, Shinji

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H05K1/0218 ,  H01L23/36 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/32 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K1/0243 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/09772 ,  H05K2201/10666 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/2036

Abstract: A mounting structure for an integrated circuit device comprises a first substrate, a second substrate and an insulator. The first substrate contains conductive wiring electrically connected to the integrated circuit device. The first substrate is mounted on the second substrate which have a ground pattern. The insulator is provided between the conductive wiring and the ground pattern.

Abstract translation: 一种用于集成电路器件的安装结构，包括第一衬底，第二衬底和绝缘体。 第一基板包含电连接到集成电路器件的导电布线。 第一衬底安装在具有接地图案的第二衬底上。 绝缘体设置在导电布线和接地图案之间。

公开(公告)号：EP0804053A1

公开(公告)日：1997-10-29

申请号：EP96118943.8

申请日：1996-11-27

Applicant: ROBERT BOSCH GMBH

Inventor： Schilling, Wolfgang

IPC: H05K1/02 ,  H05K7/20

CPC classification number: H05K1/0209 ,  H05K3/245 ,  H05K3/3452 ,  H05K2201/0209 ,  H05K2201/035 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10689

Abstract: Bei einem insbesondere als Leiterplatte (1) ausgestalteten Baugruppenträger mit wärmeerzeugenden Bauelementen, Leiterbahnen und einer über den stromführenden Leiterbahnen aufgebrachten Wärmeleitpaste, kann die Wärmeableitung dadurch verbessert werden, daß die Wärmeleitpaste (7) direkt auf den stromführenden Leiterbahnen (5) aufgebracht ist. Zur Vermeidung eines Kurzschlusses zwischen den stromführenden Leiterbahnen (5) ist vorgesehen, die Wärmeleitpaste in Form von räumlich und elektrisch voneinander getrennten, den einzelnen stromführenden Leiterbahnen zugeordneten Strukturen (7) auf den stromführenden Leiterbahnen (5) im Siebdruckverfahren aufzudrucken. Die Wärmeableitung kann noch weiter verbessert werden, wenn zusätzlich zu den stromführenden Leiterbahnen nicht stromführende Leiterbahnen (6) auf dem Baugruppenträger unterhalb der Bauelemente (2) vorgesehen sind, die ebenfalls mit Wärmeleitpaste (7) großflächig bedruckt sind.

Abstract translation: 载体（1）具有施加在导电轨道上的电流导电轨道（5）和导热膏（7）。 该浆料直接施加到轨道，并且存在用于防止轨道之间的短路的布置。 用于防止短路的装置包括将糊状物设置在导电轨道上的电气和空间上分离的结构并与各个轨迹相关联。

公开(公告)号：EP0654799A1

公开(公告)日：1995-05-24

申请号：EP94105581.6

申请日：1994-04-11

Applicant: Isabellenhütte Heusler GmbH KG

Inventor： Hetzler, Ullrich, Dr.

IPC: H01C1/14 ,  H01C7/00 ,  H01C1/144

CPC classification number: H01C1/142 ,  H01C1/084 ,  H01C13/02 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09281 ,  H05K2201/09772 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2203/162 ,  H05K2203/167 ,  Y02P70/611 ,  Y10T29/49099

Abstract: Ein Widerstand in SMD-Bauweise enthält als Widerstandsbahn (15) eine Folie aus einer Widerstandslegierung auf zwei elektrisch getrennten Trägerplattenelementen (10A,10B) aus Kupfer, die als auf die Anschlußleiter einer Leiterplatte auflötbare Kontaktelemente ausgebildet sind und dadurch für eine gute Wärmeableitung in die Leiterplatte sorgen. Zur Herstellung solcher Widerstände wird eine für eine Vielzahl einzelner Widerstände ausreichende Widerstandsfolie auf ein entsprechend großes Kupferblech geklebt, und das dadurch gebildete Laminat wird erst nach Erzeugung der einzelnen Widerstandsbahnen und deren elektrischer Verbindung mit dem Kupferblech und nach Erzeugung der Spalte (11) zwischen den Plattenelementen (10A, 10B) in die einzelnen Widerstände zerteilt.

Abstract translation: 在SMD结构的电阻器包含作为一个电阻轨道（15），电阻合金的膜，两个电分离的载体板的元件（10A，10B）由铜制成的，其被配置为表面安装到电路板接触元件的连接导体，从而为在所述电路板上的良好的散热 担心。 用于制备这样的电阻器是足够的多个单独的电阻器的电阻箔片被接合到相应的大的铜板材，并且仅生成单个电阻轨道和它们与铜板​​电连接后和生成所述板件之间的柱（11）的后这样形成的层压体是 （10A，10B）分割成单独的电阻器。