公开(公告)号：EP0768712A3

公开(公告)日：1999-01-07

申请号：EP96116327.6

申请日：1996-10-11

Applicant: MEIKO ELECTRONICS CO., LTD. ,  Machine Active Contact Co., Ltd.

Inventor： Shingai, Noboru ,  Wada, Tatsuo, c/o Meiko Electronics Co., Ltd. ,  Aoshima, Katsuro

IPC: H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15192 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2203/0338 ,  Y10T29/49155 ,  H01L2224/29099

Abstract: Provided is a circuit board, which is formed with bump patterns subject to a narrow variation in height on its surface, and permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.

公开(公告)号：EP0602609B1

公开(公告)日：1997-09-03

申请号：EP93120154.5

申请日：1993-12-14

Applicant: Hughes Aircraft Company

Inventor： Sobhani, Mohi

IPC: H01R23/72 ,  H05K3/40

CPC classification number: H01R12/61 ,  H01R12/613 ,  H01R12/62 ,  H05K1/0393 ,  H05K3/281 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0382 ,  Y10T29/49155

公开(公告)号：EP0529578B1

公开(公告)日：1996-01-31

申请号：EP92114445.7

申请日：1992-08-25

Applicant: Hughes Aircraft Company

Inventor： Crumly, William R. ,  Schreiber, Christopher M. ,  Swarbrick, David B.

IPC: H05K3/20 ,  H05K3/40

CPC classification number: G01R1/073 ,  H05K3/205 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10666 ,  H05K2203/0113 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/167

公开(公告)号：EP0533198A3

公开(公告)日：1995-11-02

申请号：EP92116025.5

申请日：1992-09-18

Applicant: NITTO DENKO CORPORATION

Inventor： Hino, Atsushi, c/o Nitto Denko Corporation ,  Mochizuki, Amane, c/o Nitto Denko Corporation ,  Ouchi, Kazuo, c/o Nitto Denko Corporation ,  Morita, Shoji, c/o Nitto Denko Corporation ,  Naito, Toshiki, c/o Nitto Denko Corporation ,  Higashi, Kazumi, c/o Nitto Denko Corporation ,  Maeda, Masako, c/o Nitto Denko Corporation ,  Kaneto, Masayuki, c/o Nitto Denko Corporation ,  Tanaka, Munekazu, c/o Nitto Denko Corporation ,  Sugimoto, Masakazu, c/o Nitto Denko Corporation

IPC: H05K1/03 ,  H05K3/40 ,  H05K3/28 ,  H05K3/46 ,  H05K3/20

CPC classification number: H05K3/4635 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K1/0346 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/0035 ,  H05K3/205 ,  H05K3/28 ,  H05K3/281 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4617 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/068 ,  H05K2201/09481 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0376 ,  H05K2203/063 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/107 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24942 ,  Y10T428/31721 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The flexible printed substrate comprises an insulating resin layer comprising a low-linear expansion polyimide resin layer (2) and a thermoplastic polyimide resin layer (3), and a metal layer (1) or a wiring circuit formed on the low-linear expansion polyimide resin layer (2) of the insulating resin layer, wherein a mixed region of the polyimide resin components is formed in the interface between the low-linear expansion polyimide resin layer (2) and the thermoplastic polyimide resin layer (3). A flexible printed substrate imparted with an adhesive property for loading on an external substrate, a double printed substrate having formed on both surfaces thereof a metal layer or a wiring circuit, and a multilayer substrate having a multilayer structure are disclosed.

Abstract translation: 公开了一种赋予外部基板的粘合性的柔性印刷基板，在其两面形成有金属层或布线电路的双面印刷基板以及具有多层结构的多层基板。 柔性印刷基板包括包含低线膨胀聚酰亚胺树脂层和热塑性聚酰亚胺树脂层的绝缘树脂层和形成在绝缘树脂层的低线膨胀聚酰亚胺树脂层上的金属层或布线电路，其中 在低线膨胀聚酰亚胺树脂层和热塑性聚酰亚胺树脂层之间的界面形成聚酰亚胺树脂成分的混合区域。

公开(公告)号：EP0653105A1

公开(公告)日：1995-05-17

申请号：EP93917226.0

申请日：1993-07-16

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： TEAD, Stanley, F. ,  ZNAMEROSKI, Stephen, J.

IPC: H01L21 ,  H05K3

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An electronic device having a plurality of electrodes is prepared for bonding with another electronic device by positioning metal bumps surrounded by a resin on selected electrodes. The bumps are then diamond turned to that the outer surfaces of all of them lie substantially in a plane. The resin is then removed.

公开(公告)号：EP0609861A3

公开(公告)日：1995-01-04

申请号：EP94101559.6

申请日：1994-02-02

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Nakamura, Yoshifumi ,  Bessho, Yoshihiro ,  Yuhaku, Satoru ,  Hakotani, Yasuhiko ,  Itagaki, Minehiro ,  Miura, Kazuhiro

IPC: H01L21/48

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4867 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/035 ,  H05K2201/0367 ,  Y10T29/49163 ,  Y10T428/24273 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00014

Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming layer; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.

公开(公告)号：EP0459665B1

公开(公告)日：1994-12-07

申请号：EP91304414.5

申请日：1991-05-16

Applicant: International Business Machines Corporation

Inventor： Murakami, Takahiro

IPC: H05K3/46

CPC classification number: H05K3/243 ,  H01L2224/81191 ,  H05K3/064 ,  H05K3/4647 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0505 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156

公开(公告)号：EP0622981A1

公开(公告)日：1994-11-02

申请号：EP94106471.9

申请日：1994-04-26

Applicant: Hitachi Chemical Co., Ltd.

Inventor： Fukutomi, Noaki ,  Nakamura, Hidehiro ,  Nakayama, Hajime ,  Tsubomatsu, Yoshiaki ,  Nakamura, Masanori ,  Kaitou, Kouichi ,  Kuwano, Atsushi, 105 Hitachikasei-Matsushiro-House ,  Watanabe, Ituo ,  Itabashi, Masahiko

IPC: H05K3/40 ,  H03K3/06

CPC classification number: G01R1/07314 ,  H05K3/062 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726

Abstract: A wiring board for electrical tests; comprising an insulating substrate (4 and 5 in Fig. 1), wiring of predetermined pattern (2) which is embedded in the insulating substrate (4, 5), and bump electrodes (1) which are formed on the wiring (2) and which are respectively brought into contact with corresponding electrodes of an article to-be-tested. Thus, even when the electrode pitch of the article to-be-tested such as a semiconductor device has become smaller (for example, less than 0.1 [mm]), the electrodes (1) can be formed so as to cope with the electrical tests of the article.

Abstract translation: 用于进行电测试的布线基板; 绝缘衬底，其包括（在图4和5。1），其嵌入在所述绝缘基板预定图案（2）所有的，布线（4,5），和凸块电极（1），它们是在布线（2）形成和 它们分别接触对应的制品的待测试的电极。 因此，即使当物品的电极间距待测试：诸如半导体设备已变得更小（例如，小于0.1 [mm]的），电极（1）可被形成为与所述电应付 本文的测试。

公开(公告)号：EP0602328A3

公开(公告)日：1994-09-21

申请号：EP93115097.3

申请日：1993-09-20

Applicant: FUJITSU LIMITED

Inventor： Love, David George ,  Moresco, Larry Louis ,  Chou, William Tai-Hua ,  Horine, David Albert ,  Wong,Connie Mak ,  Beilin, Solomon Isaac

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H05K3/4007 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/113 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H05K2203/072 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00

Abstract: An interconnect structure for connecting an integrated circuit (IC) chip (70) to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip (70) and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post (14) disposed on one of its surfaces (13) and a second post (80) disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top (18) and bottom ends (17), with the bottom end being mounted to one of the substrate surfaces (13) and the top end (18) having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means (22) for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one another so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

公开(公告)号：EP0602328A2

公开(公告)日：1994-06-22

申请号：EP93115097.3

申请日：1993-09-20

Applicant: FUJITSU LIMITED

Inventor： Love, David George ,  Moresco, Larry Louis ,  Chou, William Tai-Hua ,  Horine, David Albert ,  Wong,Connie Mak ,  Beilin, Solomon Isaac

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H05K3/4007 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/113 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H05K2203/072 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00

Abstract: An interconnect structure for connecting an integrated circuit (IC) chip (70) to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip (70) and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post (14) disposed on one of its surfaces (13) and a second post (80) disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top (18) and bottom ends (17), with the bottom end being mounted to one of the substrate surfaces (13) and the top end (18) having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means (22) for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one another so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

Abstract translation: 描述了用于将集成电路（IC）芯片（70）连接到支撑基板的互连结构。 支撑衬底用于在IC芯片（70）和诸如其他IC芯片的“外部世界”之间传送信号。 在一个实施例中，互连结构包括具有设置在其一个表面（13）上的第一柱（14）和布置在其另一表面上的第二柱（80）的互连衬底。 一个柱子用于接触IC芯片，另一个用于接触主要基板。 每个柱包括具有顶部（18）和底端（17）的细长体，其底端安装到其中一个衬底表面（13）和顶端（18），其具有基本平坦的表面， 刨床与基材表面。 互连基板还包括用于对存在于每个柱的顶端和底端的一个或两个上的机械污渍进行去浓缩的装置（22）。 第一和第二柱彼此电耦合，使得电信号可以从IC芯片传递到支撑衬底，反之亦然。