公开(公告)号：EP3042390A4

公开(公告)日：2017-04-12

申请号：EP13892844

申请日：2013-09-04

申请人： INTEL CORP ,  GOEL NITI ,  PATHI PRAGYANSRI ,  DASGUPTA SANSAPTAK ,  POWERS JAMES M ,  CHU-KUNG BENJAMIN ,  CHAU ROBERT S

发明人： MUKHERJEE NILOY ,  GOEL NITI ,  GARDNER SANAZ K ,  PATHI PRAGYANSRI ,  METZ MATTHEW V ,  DASGUPTA SANSAPTAK ,  SUNG SEUNG HOON ,  POWERS JAMES M ,  DEWEY GILBERT ,  CHU-KUNG BENJAMIN ,  KAVALIEROS JACK T ,  CHAU ROBERT S

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：EP3161854A4

公开(公告)日：2018-05-30

申请号：EP14896073

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ASKSAMIT RANDY J

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

公开(公告)号：EP3161840A4

公开(公告)日：2018-05-23

申请号：EP14895620

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ROY ANSHUMALI ,  YIP JOSEPH C

IPC分类号： H01F17/00 ,  G03F7/20 ,  H01F41/04 ,  H01G4/012 ,  H01G4/32 ,  H01G4/40 ,  H01L49/02

CPC分类号： H01L23/66 ,  G03F7/2059 ,  H01F17/0006 ,  H01F41/042 ,  H01G4/012 ,  H01G4/40 ,  H01L28/10 ,  H01L28/60 ,  H01L2223/6672

摘要： Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.

公开(公告)号：EP2901484A4

公开(公告)日：2016-10-12

申请号：EP13841467

申请日：2013-06-12

申请人： INTEL CORP

发明人： DASGUPTA SANSAPTAK ,  THEN HAN WUI ,  RADOSAVLJEVIC MARKO ,  MUKHERJEE NILOY ,  GOEL NITI ,  KABEHIE SANAZ ,  SUNG SEUNG HOON ,  PILLARISETTY RAVI ,  CHAU ROBERT S

IPC分类号： H01L29/778 ,  H01L21/223 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  H01L29/08 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

公开(公告)号：EP3050111A4

公开(公告)日：2017-06-07

申请号：EP13894331

申请日：2013-09-27

申请人： INTEL CORP

发明人： MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  KAVALIEROS JACK T ,  PILLARISETTY RAVI ,  GOEL NITI ,  LE VAN H ,  DEWEY GILBERT ,  CHU-KUNG BENJAMIN

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC分类号： H01L29/7853 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02538 ,  H01L29/0673 ,  H01L29/0688 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/78696

摘要： An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

摘要翻译： 一种设备，包括：半导体本体，包括沟道区和布置在沟道区的相对侧上的结区，半导体本体包括具有第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在延伸穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及布置在沟道区上的栅极叠层。 一种方法，包括：在衬底上方的分开的平面中形成多个纳米线，所述多个纳米线中的每一个纳米线包括包含第一带隙的材料; 在所述多个纳米线中的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 并在该包层材料上设置栅叠层。

公开(公告)号：EP3050092A4

公开(公告)日：2017-05-03

申请号：EP13894917

申请日：2013-09-27

申请人： INTEL CORP

发明人： GOEL NITI ,  CHAU ROBERT S ,  KAVALIEROS JACK T ,  CHU-KUNG BENJAMIN ,  METZ MATTHEW V ,  MUKHERJEE NILOY ,  ZELICK NANCY M ,  DEWEY GILBERT ,  RACHMADY WILLY ,  RADOSAVLJEVIC MARKO ,  LE VAN H ,  PILLARISETTY RAVI ,  DASGUPTA SANSAPTAK

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

摘要翻译： 单鳍或一对的共整合n型和p型单晶电子装置翅片外延从表面基材在一个的底部或一对浅沟槽隔离（STI）区域之间形成的沟槽的生长。 翅片或散热片被图案化和STI区域被蚀刻以形成上述的STI区的蚀刻顶表面延伸的翅片或翼片的高度。 翅片高度可以是至少1.5倍的宽度。 暴露的侧壁表面和每个翅片的顶表面上外延与一种或多种适形外延材料包覆，以形成在鳍的器件层。 之前生长翅片，毯子缓冲外延材料可从表面衬底上生长; 和在STI生长翅片沟槽的覆盖层的上方形成。 翅片的搜索形成降低从材料界面的晶格失配的缺陷。

公开(公告)号：EP2382667A4

公开(公告)日：2014-01-15

申请号：EP09836962

申请日：2009-12-17

申请人： INTEL CORP

发明人： GOEL NITI ,  TSAI WILMAN ,  KAVALIEROS JACK

IPC分类号： H01L29/739

CPC分类号： H01L29/7391 ,  H01L29/205 ,  H01L29/66356

公开(公告)号：EP3161866A4

公开(公告)日：2018-03-14

申请号：EP14895959

申请日：2014-06-27

申请人： INTEL CORP

发明人： BOU GHAZALE SILVIO E ,  ELSAYED RANY T ,  GOEL NITI

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L27/0629 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.

公开(公告)号：EP3050091A4

公开(公告)日：2017-05-10

申请号：EP13894881

申请日：2013-09-27

申请人： INTEL CORP

发明人： PILLARISETTY RAVI ,  DASGUPTA SANSAPTAK ,  GOEL NITI ,  LE VAN H ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  METZ MATTHEW V ,  RACHMADY WILLY ,  KAVALIEROS JACK T ,  CHU-KUNG BENJAMIN ,  KENNEL HAROLD W ,  CEA STEPHEN M ,  CHAU ROBERT S

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

摘要翻译： 描述了具有最大顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的半导体鳍片。 半导体鳍状物具有沿着半导体鳍状物的长度与一对突出外部分隔开的中央突出或凹陷部分。 覆层层区域设置在半导体鳍片的中央突出或凹陷部分上。 栅极叠层设置在包层区域上。 源极/漏极区域设置在半导体鳍状物的一对突出的外部区段中。

公开(公告)号：EP2901490A4

公开(公告)日：2016-06-15

申请号：EP13842724

申请日：2013-06-24

申请人： INTEL CORP

发明人： PILLARISETTY RAVI ,  GOEL NITI ,  THEN HAN WUI ,  LE VAN H ,  RACHMADY WILLY ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  CHU-KUNG BENJAMIN

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/78696