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    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP
    4.
    发明公开
    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP 有权
    工艺用于生产具有化学机械抛光非平面膜

    公开(公告)号：EP2697156A1

    公开(公告)日：2014-02-19

    申请号：EP12716951.4

    申请日：2012-04-13

    Applicant: Robert Bosch GmbH

    Inventor： GRAHAM, Andrew, B. ,  YAMA, Gary ,  O'BRIEN, Gary

    IPC: B81C1/00

    CPC classification number: B81C1/00103 ,  B81B2203/0376 ,  B81C2201/0104

    Abstract: A method of shaping a substrate in one embodiment includes providing a first support layer, providing a first shaping pattern on the first support layer, providing a substrate on the first shaping pattern, performing a first chemical mechanical polishing (CMP) process on the substrate positioned on the first shaping pattern, and removing the once polished substrate from the first shaping pattern.

    PROCESS FOR FILLING ETCHED HOLES
    5.
    发明公开
    PROCESS FOR FILLING ETCHED HOLES 审中-公开
    填充蚀刻孔的过程

    公开(公告)号：EP3259134A1

    公开(公告)日：2017-12-27

    申请号：EP16702736.6

    申请日：2016-02-03

    Applicant: Memjet Technology Limited

    Inventor： NORTH, Angus ,  O'REILLY, Ronan ,  MCAVOY, Gregory

    IPC: B41J2/16 ,  B81C1/00

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    METHOD OF MANUFACTURING A SEMICONDUCTOR ACCELEROMETER
    8.
    发明授权
    METHOD OF MANUFACTURING A SEMICONDUCTOR ACCELEROMETER 失效
    用于生产半导体加速度传感器

    公开(公告)号：EP0606220B1

    公开(公告)日：1997-03-26

    申请号：EP92914941.7

    申请日：1992-06-12

    Applicant: HARRIS CORPORATION

    Inventor： BEITMAN, Bruce, A.

    IPC: G01P15/12

    CPC classification number: B81C1/0015 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/019 ,  B81C2201/0191 ,  G01P15/0802 ,  G01P2015/0828

    Abstract: A semiconductor accelerometer is formed by attaching a semiconductor layer to a handle wafer by a thick oxide layer. Accelerometer geometry is patterned in the semiconductor layer, which is then used as a mask to etch out a cavity in the underlying thick oxide. The mask may include one or more apertures, so that a mass region will have corresponding apertures to the underlying oxide layer. The structure resulting from an oxide etch has the intended accelerometer geometry of a large volume mass region supported in cantilever fashion by a plurality of piezo-resistive arm regions to a surrounding, supporting portion of the semiconductor layer. Directly beneath this accelerometer geometry is a flex-accommodating cavity realized by the removal of the underlying oxide layer. The semiconductor layer remains attached to the handle wafer by means of the thick oxide layer that surrounds the accelerometer geometry, and which was adequately masked by the surrounding portion of the top semiconductor layer during the oxide etch step. In a second embodiment support arm regions are dimensioned separately from the mass region, using a plurality of buried oxide regions as semiconductor etch stops.

    CMP PROCESS FLOW FOR MEMS
    9.
    发明公开
    CMP PROCESS FLOW FOR MEMS 有权
    CMP处理流程MEMS

    公开(公告)号：EP2542499A2

    公开(公告)日：2013-01-09

    申请号：EP11707299.1

    申请日：2011-02-25

    Applicant: Cavendish Kinetics Inc.

    Inventor： LACEY, Joseph Damian Gordon ,  MAGUIRE, Thomas L. ,  JOSHI, Vikram ,  YOST, Dennis J.

    IPC: B81C1/00

    CPC classification number: B81C1/00095 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0104

    Abstract: The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：EP2219215A1

    公开(公告)日：2010-08-18

    申请号：EP08864653.4

    申请日：2008-12-12

    Applicant: Fujikura, Ltd.

    Inventor： YAMAMOTO, Satoshi ,  HASHIMOTO, Hirokazu

    IPC: H01L23/02 ,  H01L27/14 ,  H01L29/84 ,  B81C3/00

    CPC classification number: B81C1/00317 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0125 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor device includes: a bonding step of bonding a first substrate with optical transparency and a second substrate having a surface on which a functional element is provided to each other such that the functional element faces the first substrate; a thinning step of thinning at least one of the first and second substrates; and a through-hole forming step of forming a cavity and a through-hole communicated with the cavity in at least part of a bonding portion between the first and second substrates. According to the present invention, it is possible to prevent irregularities or cracks caused by the presence or absence of the cavity and more regularly thin the substrate. In addition, it is possible to manufacture a semiconductor device capable of contributing to the miniaturization of devices and electronic equipment having the devices, using a more convenient process.

    Abstract translation: 一种制造半导体器件的方法包括：键合步骤，将具有光学透明性的第一基板和具有其上设置有功能元件的表面的第二基板彼此键合，使得功能元件面向第一基板; 减薄第一和第二基板中的至少一个的减薄步骤; 以及通孔形成步骤，在第一和第二基板之间的接合部分的至少一部分中形成腔体和与腔体连通的通孔。 根据本发明，可以防止由空腔的存在或不存在引起的不规则或裂缝，并且更规则地使基板变薄。 此外，可以使用更便利的工艺来制造能够有助于装置和具有该装置的电子设备的小型化的半导体装置。

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