Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage
    1.
    发明授权
    Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage 有权
    在暴露的低k表面上形成含SiOCl的层以降低低k损伤

    公开(公告)号:US08592327B2

    公开(公告)日:2013-11-26

    申请号:US13413878

    申请日:2012-03-07

    IPC分类号: H01L21/31 H01L21/469

    摘要: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.

    摘要翻译: 描述了一种用于保护暴露的低k表面的方法。 该方法包括接收具有掩模层和形成在其上的低k层的衬底,其中使用光刻工艺在掩模层中形成的图案已经使用蚀刻工艺转移到低k层,以在其中形成结构特征 。 此外,该方法包括在掩模层和低k层的暴露表面上形成含SiOCl的层,并且从掩模层的顶表面和结构特征的底表面各向异性除去含SiOCl层 同时在结构特征的侧壁表面上保留含SiOCl层的剩余部分。 该方法还包括进行灰化处理以除去掩模层,然后从结构特征的侧壁表面选择性地除去含SiOCl层的剩余部分。

    FORMATION OF SiOCl-CONTAINING LAYER ON EXPOSED LOW-K SURFACES TO REDUCE LOW-K DAMAGE
    2.
    发明申请
    FORMATION OF SiOCl-CONTAINING LAYER ON EXPOSED LOW-K SURFACES TO REDUCE LOW-K DAMAGE 有权
    在暴露的低K表面上形成含有SiOCl的层以减少低K损伤

    公开(公告)号:US20130237060A1

    公开(公告)日:2013-09-12

    申请号:US13413878

    申请日:2012-03-07

    IPC分类号: H01L21/311

    摘要: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.

    摘要翻译: 描述了一种用于保护暴露的低k表面的方法。 该方法包括接收具有掩模层和形成在其上的低k层的衬底,其中使用光刻工艺在掩模层中形成的图案已经使用蚀刻工艺转移到低k层,以在其中形成结构特征 。 此外,该方法包括在掩模层和低k层的暴露表面上形成含SiOCl的层,并且从掩模层的顶表面和结构特征的底表面各向异性除去含SiOCl层 同时在结构特征的侧壁表面上保留含SiOCl层的剩余部分。 该方法还包括进行灰化处理以除去掩模层,然后从结构特征的侧壁表面选择性地除去含SiOCl层的剩余部分。

    SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERCONNECT PATTERNING
    4.
    发明申请
    SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERCONNECT PATTERNING 有权
    用于互连图案的硬掩模拆卸期间的边框和顶部保护

    公开(公告)号:US20130236989A1

    公开(公告)日:2013-09-12

    申请号:US13414015

    申请日:2012-03-07

    IPC分类号: H01L21/66

    摘要: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

    摘要翻译: 描述了用于去除硬掩模的方法的方法。 该方法包括使用一个或多个蚀刻工艺和覆盖低k绝缘层的硬掩模层,在衬底上的低k绝缘层中形成沟槽通孔结构的至少一部分。 此后,该方法包括在沟槽通孔结构的暴露表面上沉积含SiOCl的层以形成绝缘保护层,执行一个或多个蚀刻工艺以使至少一部分含SiOCl层从至少一个 沟槽通孔结构的表面,并且使用掩模去除蚀刻工艺去除硬掩模层。

    AN IMPROVED CORONARY STENT DELIVERY SYSTEM FOR BIFURCATION LESIONS

    公开(公告)号:US20210145615A1

    公开(公告)日:2021-05-20

    申请号:US16623222

    申请日:2018-06-15

    申请人: Alok RANJAN

    发明人: Alok RANJAN

    IPC分类号: A61F2/856 A61F2/958 A61F2/954

    摘要: The invention relates to an improved coronary stent delivery system to address bifurcation lesion, a modification (channel) in stent 5 delivery system. The said system comprises steps a) to accommodate an extra PTCA wire between the stent and the underlying balloon with first wire in the main branch (MB) port and the side branch wire in channel provided for it in between stent and underlying balloon; b) load the stent on the MB wire and also pass 10 the SB wire in the channel provided for it so that once stent is inflated in the main branch and the balloon is removed after inflation, the side branch is accessible as there is SB wire is already inside the stent; c) another balloon or stent to be used to open the side branch in case there is serious compromise in flow in 15 side branch or if 2 stents strategy is planned.

    Method for reducing damage to low-k gate spacer during etching
    6.
    发明授权
    Method for reducing damage to low-k gate spacer during etching 有权
    在蚀刻期间减少对低k栅极间隔物的损伤的方法

    公开(公告)号:US09111746B2

    公开(公告)日:2015-08-18

    申请号:US13589096

    申请日:2012-08-18

    摘要: A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

    摘要翻译: 描述了用于执行间隔物蚀刻工艺的方法。 该方法包括在基板上提供栅极结构,该栅极结构具有保形施加在栅极结构上的低k间隔物材料,并且执行间隔物蚀刻工艺序列以从栅极结构和衬底部分去除间隔物材料,同时保持侧壁间隔物 沿着门结构的侧壁定位。 间隔物蚀刻工艺序列可以包括在所述间隔物材料的暴露表面上沉积隔离物保护层,并且执行一个或多个蚀刻工艺以选择性地和各向异性地去除间隔物保护层和间隔物材料以留在侧壁上的侧壁间隔物 其中,当通过一个或多个蚀刻工艺部分或完全地消耗时,间隔物保护层在组成和/或介电常数上表现出减小的变化。

    Sidewall and chamfer protection during hard mask removal for interconnect patterning
    7.
    发明授权
    Sidewall and chamfer protection during hard mask removal for interconnect patterning 有权
    用于互连图案化的硬掩模去除期间的侧壁和倒角保护

    公开(公告)号:US08551877B2

    公开(公告)日:2013-10-08

    申请号:US13414015

    申请日:2012-03-07

    IPC分类号: H01L21/4763 H01L23/532

    摘要: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

    摘要翻译: 描述了用于去除硬掩模的方法的方法。 该方法包括使用一个或多个蚀刻工艺和覆盖低k绝缘层的硬掩模层,在衬底上的低k绝缘层中形成沟槽通孔结构的至少一部分。 此后,该方法包括在沟槽通孔结构的暴露表面上沉积含SiOCl的层以形成绝缘保护层,执行一个或多个蚀刻工艺以使至少一部分含SiOCl层从至少一个 沟槽通孔结构的表面,并且使用掩模去除蚀刻工艺去除硬掩模层。

    METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE
    9.
    发明申请
    METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE 审中-公开
    使用脉冲直流电压蚀刻基板的方法

    公开(公告)号:US20120088371A1

    公开(公告)日:2012-04-12

    申请号:US13089374

    申请日:2011-04-19

    IPC分类号: H01L21/3065

    摘要: Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.

    摘要翻译: 本文提供了使用脉冲DC电压蚀刻基板的方法。 在一些实施例中,用于蚀刻设置在处理室内的衬底支撑件上的衬底的方法的方法可包括向处理室提供工艺气体; 从工艺气体形成等离子体; 向设置在处理室内的第一电极施加脉冲DC电压; 并在施加脉冲DC电压的同时刻蚀衬底。