利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

51 条记录 (耗时 0.025 秒)

    Methods and apparatuses to stiffen integrated circuit package
    2.
    发明授权
    Methods and apparatuses to stiffen integrated circuit package 有权
    强化集成电路封装的方法和装置

    公开(公告)号：US08502400B2

    公开(公告)日：2013-08-06

    申请号：US13413616

    申请日：2012-03-06

    申请人： Prasanna Karpur ,  Sriram Muthukumar

    发明人： Prasanna Karpur ,  Sriram Muthukumar

    IPC分类号： H01L23/29 ,  H01L23/48

    CPC分类号： H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.

    摘要翻译： 提出了一种用于封装衬底的大坝加强件。 在一个实施方案中，坝加强件包括可热固化的聚合物，并且与底部填充材料同时固化以作为基底的加强件。 在另一个实施例中，可以分配可固化储存器材料以填充集成电路管芯和坝加强件之间的空间，形成用作封装衬底的附加加强件的厚的储存层。

    Methods for making multi-chip packaging using an interposer
    3.
    发明授权
    Methods for making multi-chip packaging using an interposer 有权
    使用插入片进行多芯片封装的方法

    公开(公告)号：US08387240B2

    公开(公告)日：2013-03-05

    申请号：US12955816

    申请日：2010-11-29

    申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    IPC分类号： H01K3/10

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

    摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

    摘要翻译： 在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。 电绝缘层形成在主体的侧壁和上表面上。 在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的 间距比第一金属垫。 在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。 身体通过下表面变薄，并且通孔中的电绝缘层被暴露。 在变薄之后，去除通孔中的电绝缘层的一部分。 主体耦合到基板。

    Look-up table overdrive circuits
    5.
    发明授权
    Look-up table overdrive circuits 有权
    查找表超速电路

    公开(公告)号：US07800402B1

    公开(公告)日：2010-09-21

    申请号：US11982865

    申请日：2007-11-05

    申请人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

    发明人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

    摘要翻译： 可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。 数据信号可以通过互连路由到其他逻辑电路。 互连可以是可编程的。 可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。 连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。 可以提供电平移位电路以升高互连上的数据信号。 每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。 升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

    Process for coating thick resist over polymer features
    8.
    发明申请
    Process for coating thick resist over polymer features 审中-公开
    在聚合物特征上涂覆厚抗蚀剂的方法

    公开(公告)号：US20060286487A1

    公开(公告)日：2006-12-21

    申请号：US11158168

    申请日：2005-06-20

    申请人： Charles Hill ,  Sriram Muthukumar ,  Patrick Dunaway

    发明人： Charles Hill ,  Sriram Muthukumar ,  Patrick Dunaway

    IPC分类号： G03F7/26

    CPC分类号： G03F7/0035 ,  H05K3/108 ,  H05K3/4092 ,  H05K2203/054 ,  H05K2203/308

    摘要： An embodiment of a process is disclosed comprising depositing a sealing layer on a first photoresist layer formed on a substrate, the first photoresist layer having a form patterned and etched therein, depositing a second photoresist layer on the sealing layer, and curing the second photoresist layer by changing its temperature from a first temperature to a second temperature over a set period of time. An embodiment of an apparatus is disclosed comprising a substrate having a first photoresist layer thereon, the first photoresist layer having a form patterned and etched therein, a sealing layer deposited on the first photoresist layer, and a second photoresist layer on the sealing layer, wherein the second photoresist layer is cured by changing its temperature from a first temperature to a second temperature over a set period of time. Other embodiments are disclosed and claimed.

    摘要翻译： 公开了一种方法的实施方案，包括在形成在基底上的第一光致抗蚀剂层上沉积密封层，第一光致抗蚀剂层具有图案化和蚀刻在其中的形式，在密封层上沉积第二光致抗蚀剂层，并固化第二光致抗蚀剂层 通过在一段时间内将其温度从第一温度改变到第二温度。 公开了一种装置的实施例，包括其上具有第一光致抗蚀剂层的基底，第一光致抗蚀剂层具有图案化和蚀刻的形式，沉积在第一光致抗蚀剂层上的密封层和密封层上的第二光致抗蚀剂层，其中 第二光致抗蚀剂层通过在一段设定的时间段内将温度从第一温度改变到第二温度来固化。 公开和要求保护其他实施例。