公开(公告)号：US09136241B2

公开(公告)日：2015-09-15

申请号：US13446954

申请日：2012-04-13

申请人： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L23/04 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10

CPC分类号： H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

摘要翻译： 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。

公开(公告)号：US08624383B2

公开(公告)日：2014-01-07

申请号：US12836477

申请日：2010-07-14

申请人： Yu-Lin Yen ,  Chen-Mei Fan

发明人： Yu-Lin Yen ,  Chen-Mei Fan

IPC分类号： H01L23/12

CPC分类号： H01L27/14618 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14

摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

摘要翻译： 本发明提供一种集成电路封装及其制造方法。 集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。 阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

公开(公告)号：US08575634B2

公开(公告)日：2013-11-05

申请号：US12981600

申请日：2010-12-30

申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC分类号： H01L33/60 ,  H01L33/48

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

公开(公告)号：US20110285032A1

公开(公告)日：2011-11-24

申请号：US13204603

申请日：2011-08-05

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC分类号： H01L23/498

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，位于孔中并与导电焊盘电接触。

公开(公告)号：US08003442B2

公开(公告)日：2011-08-23

申请号：US11878568

申请日：2007-07-25

申请人： Yu-Lin Yen ,  Chen-Mei Fan

发明人： Yu-Lin Yen ,  Chen-Mei Fan

IPC分类号： H01L21/00

CPC分类号： H01L27/14618 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14

摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

摘要翻译： 本发明提供一种集成电路封装及其制造方法。 集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。 阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

公开(公告)号：US20110193241A1

公开(公告)日：2011-08-11

申请号：US13024156

申请日：2011-02-09

申请人： Yu-Lin YEN ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin YEN ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

摘要翻译： 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。

公开(公告)号：US20070166946A1

公开(公告)日：2007-07-19

申请号：US11715527

申请日：2007-03-07

申请人： Yu-Lin Yen ,  Ching-Yu Chang

发明人： Yu-Lin Yen ,  Ching-Yu Chang

IPC分类号： H01L21/762 ,  H01L23/544

CPC分类号： G03F9/7003 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

公开(公告)号：US07196429B2

公开(公告)日：2007-03-27

申请号：US10833206

申请日：2004-04-26

申请人： Yu-Lin Yen ,  Ching-Yu Chang

发明人： Yu-Lin Yen ,  Ching-Yu Chang

IPC分类号： H01L21/76 ,  H01L23/544

CPC分类号： G03F9/7003 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

摘要翻译： 公开了尽管轮廓偏移的能够运行的集成电路。 集成电路上的覆盖标记被沟槽包围，该沟槽倾向于减轻由施加到集成电路的应力引起的轮廓移位的影响。 因此，覆盖标记的位置倾向于不受应力的影响。

公开(公告)号：US20060094232A1

公开(公告)日：2006-05-04

申请号：US10976539

申请日：2004-10-29

申请人： Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

发明人： Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/7685

摘要： A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

摘要翻译： 提供了一种形成半导体器件的方法，该半导体器件通过在金属层上并入多层抗反射涂层来减少金属应力诱导的光失准。 该方法包括：在衬底上形成导电层的衬底，沉积多层抗反射涂层（包括钛和氮化钛的交替层），与第一蚀刻步骤相结合形成多条导电线，沉积 介电层，并且与第二蚀刻步骤相关地限定至少一个通孔。

公开(公告)号：US08536671B2

公开(公告)日：2013-09-17

申请号：US13154337

申请日：2011-06-06

申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC分类号： H01L31/0203

CPC分类号： H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

摘要翻译： 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。