Reducing charging effects in charged-particle-beam lithography
    1.
    发明授权
    Reducing charging effects in charged-particle-beam lithography 失效
    减少带电粒子束光刻中的充电效应

    公开(公告)号:US4323638A

    公开(公告)日:1982-04-06

    申请号:US178988

    申请日:1980-08-18

    IPC分类号: H01L21/027 B05D3/06

    摘要: In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.

    摘要翻译: 在带电粒子束光刻系统中,对准或写入期间工件上的电荷累积可能导致显着的图案放置误差。 在光刻过程中,作为导电介质,利用形成在图案化抗蚀剂层(56)正下方的膜(16)。 在抗蚀剂层(56)中描绘的图案被转移到膜(16)中并随后转移到下层(20)中。 薄膜(16)与用于制造LSI和VLSI电路的标准光刻和蚀刻工艺高度兼容。

    Method of determining a dechucking voltage which nullifies a residual
electrostatic force between an electrostatic chuck and a wafer
    6.
    发明授权
    Method of determining a dechucking voltage which nullifies a residual electrostatic force between an electrostatic chuck and a wafer 失效
    确定脱扣电压的方法,其消除静电卡盘和晶片之间的剩余静电力

    公开(公告)号:US5491603A

    公开(公告)日:1996-02-13

    申请号:US235012

    申请日:1994-04-28

    CPC分类号: H01L21/6833

    摘要: The invention is embodied in a method of determining an optimum de-chucking voltage for nullifying residual electrostatic forces on a wafer in an electrostatic chuck for removal of the wafer from the chuck, including holding the wafer on the electrostatic chuck by applying an electrostatic potential to the chuck, introducing a gas between the wafer and the chuck, reducing the electrostatic potential of the chuck while observing a rate of leakage of the gas from between the wafer and the chuck, and recording as the optimum dechucking voltage the value of the electrostatic potential obtaining when the rate of leakage exceeds a predetermined threshold.

    摘要翻译: 本发明体现于一种确定最佳去夹紧电压的方法,用于使静电卡盘中的晶片上的残留静电力无效,从卡盘移除晶片,包括通过施加静电电位将晶片保持在静电卡盘上 卡盘,在晶片和卡盘之间引入气体,同时观察卡盘的气体泄漏速率,同时减小卡盘的静电电位,并记录最佳的脱扣电压为静电电位值 当泄漏速率超过预定阈值时获得。

    Devices having tantalum silicide structures
    7.
    发明授权
    Devices having tantalum silicide structures 失效
    具有硅化钽结构的器件

    公开(公告)号:US4937643A

    公开(公告)日:1990-06-26

    申请号:US78013

    申请日:1987-07-27

    IPC分类号: H01L21/28 H01L21/3213

    CPC分类号: H01L21/32137 H01L21/28061

    摘要: A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.

    摘要翻译: 公开了一种制造包括硅化钽结构并且基本上不含导电蚀刻残留物的器件的方法。 该方法包括以下步骤:将钽和硅沉积到衬底上,图案化钽和硅,然后烧结图案化的钽和硅以形成图案化的硅化钽层。