公开(公告)号：US20220130953A1

公开(公告)日：2022-04-28

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11271076B2

公开(公告)日：2022-03-08

申请号：US16517222

申请日：2019-07-19

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.

公开(公告)号：US10957759B2

公开(公告)日：2021-03-23

申请号：US16235486

申请日：2018-12-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.

公开(公告)号：US10892237B2

公开(公告)日：2021-01-12

申请号：US16221033

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Liangchun Yu ,  Nancy Cecelia Stoffel ,  David Richard Esler ,  Christopher James Kapusta

IPC: H01L21/00 ,  H01L23/60 ,  H01L29/16 ,  H01L29/66 ,  H01L23/00 ,  H01L29/10 ,  H01L29/20 ,  H01L29/778

Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.

公开(公告)号：US09379189B2

公开(公告)日：2016-06-28

申请号：US14644481

申请日：2015-03-11

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Michah Sandvik ,  Stephen Daley Arthur

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/861 ,  H01L21/04 ,  H01L29/66 ,  H01L29/32

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/8618 ,  H01L2924/10272

Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract translation: 瞬态电压抑制（TVS）装置包括由第一导电类型材料形成的第一层宽带隙半导体材料，第二层宽带隙半导体材料，由第二导电类型材料形成，该第二导电类型材料在第一导电类型材料的至少一部分上 并且包括在0.1微米（μm）和22.0μm厚之间的离子注入材料结构，所述第二层使用穿透物理学操作，以及由第一导电类型材料形成的第三层宽带隙半导体材料，至少在 第二层的一部分。

公开(公告)号：US20160087091A1

公开(公告)日：2016-03-24

申请号：US14787545

申请日：2013-11-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean MATOCHA ,  Ramakrishna RAO ,  Peter Almern LOSEE ,  Alexander Viktorovich BOLOTNIKOV

IPC: H01L29/78 ,  H03K17/687 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体（200）和栅氧化层（234）。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域（216）和掺杂有相对的第二类型掺杂剂并且位于第一阱区域内的第二阱区域（220）。 栅极氧化物包括相对较薄的外部部分（244）和相对较厚的内部部分（246）。 外部部分设置在第一井区域和第二井区域上。 内部部分设置在掺杂有第二类型掺杂剂的半导体主体的结栅场效应晶体管区域（218）上。 当栅极信号施加到设置在栅极氧化物上的栅极接触（250）时，通过第二阱区形成导电沟道。

公开(公告)号：US09123798B2

公开(公告)日：2015-09-01

申请号：US13712188

申请日：2012-12-12

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。

公开(公告)号：US20130328064A1

公开(公告)日：2013-12-12

申请号：US13967886

申请日：2013-08-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

IPC: H01L21/56 ,  H01L29/16

CPC classification number: H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Abstract translation: 提供了形成碳化硅瞬态电压抑制器（TVS）组件的方法和用于瞬态电压抑制器（TVS）组件的系统。 TVS组件包括台面结构中的半导体管芯，其包括具有第一极性的导电率的第一宽带隙半导体的第一层，具有第二极导电率的第一或第二宽带隙半导体的第二层 极性与第一层电接触，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层。 相对于具有第一极性的导电性的层，具有第二极性的导电性的层被轻掺杂。

公开(公告)号：US09735263B2

公开(公告)日：2017-08-15

申请号：US14787545

申请日：2013-11-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L27/088 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.

公开(公告)号：US20150236151A1

公开(公告)日：2015-08-20

申请号：US14182765

申请日：2014-02-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： James Jay McMahon ,  Ljubisa Dragoljub Stevanovic ,  Stephen Daley Arthur ,  Thomas Bert Gorczyca ,  Richard Alfred Beaupre ,  Zachary Matthew Stum ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/045 ,  H01L21/049 ,  H01L21/28247 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7816

Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

Abstract translation: 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。